The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

An acoustic feature extraction (AFE) circuit includes a plurality of band-pass filters (BPFs) adaptable to a plurality of channels with different band-pass frequency ranges respectively for switchably receiving an amplified signal, thereby generating corresponding filtered signals, the plurality of BPFs including an operational amplifier that is shared among the plurality of channels; and a rectifier switchably coupled to receive the filtered signals, thereby generating a rectified signal. The amplified signal is time-division demultiplexed onto the BPFs in different phases, and the filtered signals are time-division multiplexed onto the rectifier in different phases.

Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A close-down pop reduction system and a method for close-down pop reduction in an audio amplifier assembly are disclosed. The switching power conversion system comprises a forward path having a compensator and a switching power stage and a signal path from an output of a comparator in the switching power stage to a sequence control unit. The signal path includes a close-down timing circuit configured to provide a timing signal. The sequence control unit is configured to eliminate the input signal, increase the switch frequency of the close-down pop reduction system and disable the switching power stage at a moment in time within a PWM pulse of the switching power stage. Hereby, it is e.g. possible to minimize the audible pop during close-down of audio amplifier assemblies.

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

A pixel circuit includes a differential amplifier. The differential amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The differential amplifier includes an input differential pair including first and second NMOS transistors, a current mirror pair including PMOS transistors, and a constant current source including a fifth NMOS transistor. A threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of the fifth NMOS transistor. Further, the threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of another NMOS transistor.

Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Methods and systems for accurate gain adjustment of a transimpedance amplifier using a dual replica and servo loop is disclosed and may include, in a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, and a third TIA, each comprising a configurable feedback impedance, and a control loop, where the control loop comprises a gain stage with inputs coupled to outputs of the first and second TIAs and an output coupled to the configurable feedback impedance of the second and third TIAs: configuring a gain level of the first TIA by configuring its feedback impedance, configuring a gain level of the third TIA by configuring a reference current applied to an input of the first TIA, and amplifying a received electrical signal to generate an output voltage utilizing the third TIA. The reference current may generate a reference voltage at one of the inputs of the gain stage.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.