A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.

A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

A radio frequency (RF) receive circuit is described herein. In accordance with one embodiment, the RF receive circuit includes a mixer configured to receive an RF input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The signal processing chain includes at least two circuit nodes. The RF receive circuit further includes an oscillator circuit that is configured to generate a test signal. The oscillator circuit is coupled to the signal processing chain and is configured to selectively feed the oscillator signal into one of the at least two circuit nodes.

According to a first aspect of the embodiments, a microphone mixer is provided comprising: an input adapted to receive differential microphone (mic) output signals; a gain-trim circuit adapted to receive the differential mic output signals, and which includes a substantially fully differential amplifier adapted to amplify the received differential mic output signals through use of a gain-trim output adjustment device that provides a variable gain amount ranging from a first gain-trim gain value to a second gain-trim gain value, to produce differential gain-trim circuit output signals; a fader circuit adapted to receive the differential gain-trim circuit output signals, and which includes a differential amplifier adapted to attenuate the received differential gain-trim circuit output signals through use of a fader output adjustment device that provides a variable gain amount ranging from a first fader gain value to a second fader value; and a common adjustment apparatus that mechanically ties the gain-trim output adjustment device with the fader output adjustment device such that the first gain-trim gain value and first fader gain value are obtained substantially simultaneously at a first position of the common adjustment apparatus, and the second gain-trim gain value and second fader gain value are obtained substantially simultaneously at a second position of the common adjustment apparatus.

A radio frequency filter includes communication bandpass filters disposed corresponding respectively to a plurality of communication bands, a switch, and a matching circuit. The switch includes a common terminal and a plurality of optionally selectable terminals, the plurality of optionally selectable terminals being individually connected to the plurality of bandpass filters in a one-to-one relation. The matching circuit is connected to the common terminal and is a common matching circuit to the plurality of communication bandpass filters. The plurality of communication bandpass filters are set such that filter characteristics of a serial circuit in combination of one of the plurality of communication bandpass filters, the one being selected by the switch, and the common matching circuit are improved in comparison with filter characteristics of the selected communication bandpass filter with respect to the communication band corresponding to the selected communication bandpass filter.

A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Improvement in heat dissipation capability is intended. A radio-frequency module includes a mounting substrate, a plurality of transmission filters, a resin layer, and a shield layer. The mounting substrate has a first major surface and a second major surface opposite to each other. The plurality of transmission filters is mounted on the first major surface of the mounting substrate. The resin layer is disposed on the first major surface of the mounting substrate and covers at least part of an outer peripheral surface of each of the plurality of transmission filters. The shield layer covers the resin layer and at least part of each of the plurality of transmission filters. At least part of a major surface of each of the plurality of transmission filters on an opposite side to the mounting substrate side is in contact with the shield layer.

A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

Thermal temperature sensors for power amplifiers are provided herein. In certain implementations, a semiconductor die includes a compound semiconductor substrate, and a power amplifier including a plurality of field-effect transistors (FETs) configured to amplify a radio frequency (RF) signal. The plurality of FETs are arranged on the compound semiconductor substrate as a transistor array. The semiconductor die further includes a semiconductor resistor configured to generate a signal indicative of a temperature of the transistor array. The semiconductor resistor is located adjacent to one end of the transistor array.