A high-frequency signal amplifier circuit is used in a front-end circuit configured to propagate a high-frequency transmission signal and a high-frequency reception signal, and includes an amplifier transistor configured to amplify the high-frequency transmission signal; a bias circuit configured to supply a bias to a signal input end of the amplifier transistor; and a ferrite bead, one end of which is connected to a bias output end of the bias circuit and the other end of which is connected to the signal input end of the amplifier transistor, having characteristics in which impedance in a difference frequency band between the high-frequency transmission signal and the high-frequency reception signal is higher than impedance in DC.

A system includes a power regulator coupled between a coil and a battery, wherein the power regulator is configured as a linear regulator when power is provided from the coil to the battery, and a current sense apparatus having two inputs coupled to an input and an output of the power regulator, respectively, wherein the current sense apparatus is configured to sense a bidirectional current flowing through the power regulator.

A bias circuit includes a current generating circuit generating an internal base current based on a reference current, a bias output circuit generating a base bias current based on the internal base current and outputting the base bias current to an amplifying circuit, and a temperature compensation circuit regulating the base bias current based on a temperature voltage reflecting a change in ambient temperature.

A dual-mode average power tracking (APT) controller operates in a first mode to move the control voltage quickly without concern for ripple or ringing. When this coarse adjustment takes the control voltage to within a desired margin of a target, the controller may switch to a second mode, where the APT controller more slowly approaches the target, but has reduced ringing or ripples. The mode is changed by changing resistance and capacitance values in a loop filter within the APT circuit. In a further aspect, a pulse shaper circuit may inject a pulse to force the control voltage to change more rapidly. By switching modes in this fashion, the control voltage may quickly reach a desired target, and then remain in the second mode during a transmission time slot such that the control voltage is clean throughout.

A circuit includes a first transistor comprising a gate, a source, and a drain, and an inductor coupled between the gate and the source of the first transistor, wherein the source is further coupled to a current source and the gate is further coupled to an amplifier.

A wide bandgap voltage reference circuit generates a temperature stable negative bias reference voltage for use in wide bandgap circuits. The reference circuit uses field effect transistor (FET) based source feedback. It can also be used as source feedback in high power high bandgap device applications, where constant current is required over process and thermal variations.

The present invention describes an amplifier adjusting device for an amplifier element which is adjustable as a function of amplification factor and is coupled to a frequency domain selecting element for adjusting at least to frequency domains. The amplifier adjusting device includes a memory in which at least two amplification factors may be stored, the at least two amplification factors being assigned to the two at least two frequency domains, an amplification factor adjusting element configured to select, depending on a current frequency domain, a corresponding amplification factor from the memory in order to adjust the adjustable amplifier element, and an amplification factor estimator configured to correct, based on an analysis of a signal amplified by means of the adjustable amplifier element in accordance with the selected amplification factor, the selected amplification factor and store the corrected amplification factor in the memory.

A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.

A quadrature modulator and the transmission unit output a modulated wave obtained by performing quadrature modulation on a carrier wave using a first I signal and a first Q signal and wirelessly transmit the modulated wave. A reception unit and the quadrature detector detect a received signal corresponding to a wireless signal transmitted from the wireless tag using the carrier wave and to output a second I signal and a second Q signal. A filter and the amplification unit amplify a frequency component higher than a cutoff frequency in the second I signal and the second Q signal. A detector and the decoding unit decode data based on a detection signal obtained by detecting the amplified second I signal and the amplified second Q signal. A generation unit generates the first I signal and the first Q signal such that the modulated wave is a signal obtained by shifting a frequency of the carrier wave by a frequency shift amount more than the cutoff frequency and to input the first I signal and the first Q signal to the quadrature modulator.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.