Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

A switch element includes a source having a plurality of source fingers and a drain having a plurality of drain fingers interleaved with the source fingers. An active mesa region is defined between at least one of the plurality of source fingers and an adjacent at least one of the plurality of drain fingers. A plurality of gates are disposed between the at least one of the plurality of source fingers and the adjacent at least one of the plurality of drain fingers. At least one of gates extends into the active mesa region from outside of the active mesa region and terminates within the active mesa region.

An optical receiver includes: a light reception element to convert an input optical signal into a first current signal and output the first current signal; an inverter-based TIA to convert the first current signal into a voltage signal and output the voltage signal using first and second field effect transistors; a current monitor unit to monitor a current magnitude of the first current signal and output a second current signal having a current magnitude based on the current magnitude of the first current signal; and a back-gate adjustment unit to determine a state of an input-output characteristic of the inverter-based TIA on the basis of the second current signal and the voltage signal, and control, on the basis of the determination result, a back-gate terminal voltage of at least one of the first and second field effect transistors.

An amplifier including: an input terminal coupled to a first node; an output terminal coupled to a second node; and a transistor coupled between a first power source and a second power source, the transistor including: a gate electrode coupled to the first node; a drain electrode coupled to the second node; a source electrode coupled to a third node; and a bulk electrode coupled to a fourth node and configured to receive a bulk voltage to change a threshold voltage of the transistor.

A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are disposed on opposite sides of the active region.

A digital power amplifier (DPA) architecture addresses power efficiency limitations in shared PA designs supporting multiple communication protocols with differing transmission power requirements. The DPA comprises PA cell arrays, with each cell including both low voltage (LV) and high voltage (HV) domain PA cells that are separately activated. For low power transmissions, LV domain cells operate while HV domain cells are placed into a high-impedance state to minimize loading and improve efficiency. For high power transmissions, both LV and HV domain cells operate to achieve desired transmit power. The architecture includes a unified combiner coupling both voltage domains, domain-specific output stages optimized for respective voltage levels, and a differential level shifter providing amplitude-preserving voltage conversion for HV domain control. This dual bias topology enables significant power efficiency improvements across wide transmission power ranges compared to conventional single-bias or Class G DPA architectures.