Patent classifications
H03F2200/18
Amplification of a radio frequency signal
Apparatus (1) comprises envelope signal amplification circuitry (11) configured to receive an input envelope signal (ENV_in) indicative of an envelope of an input radio frequency signal (RF_in) and to output an amplified envelope signal (ENV_amp); and a radio frequency power amplifier (12) configured to receive a radio frequency control signal which is dependent on the input radio frequency signal(RF_in) and the input envelope signal (ENV_in), using the amplified envelope signal (ENV_amp) as its supply voltage, to output an amplified radio frequency signal (RF_amp). A method for amplification the radio frequency signal is also provided.
Memory effect reduction using low impedance cascode biasing
A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.
ULTRA COMPACT MULTI-BAND TRANSMITTER WITH ROBUST AM-PM DISTORTION SELF-SUPPRESSION TECHNIQUES
A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
Cascode power amplifier with switchable output matching network
A radio-frequency (RF) module includes a first transistor having a base, a collector, and an emitter, a radio-frequency output transmit path coupled to the collector of the first transistor at a first end and to a radio-frequency output port at a second end, and an output matching network disposed in the radio-frequency output transmit path, the output matching network including a shunt arm coupled to ground, the shunt arm including a switch that is controllable to modify an impedance of the output matching network.
High-speed time division duplexing transceiver for wired communication and method thereof
A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.
Cascode amplifier bias circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
Voltage Supply Circuit and Power Supply Unit Delivering Constant Power
A voltage supply circuit includes a rectifier circuit, a charging circuit, a feedback circuit and an energy storage circuit. The rectifier circuit is used to receive an input voltage to generate a rectified energy. The charging circuit is coupled to the rectifier circuit and has a modulation input terminal and an energy supply terminal. The modulation input terminal is used to receive a modulation voltage, and the energy supply terminal is used to selectively output a charging current according to the modulation voltage. The feedback circuit is used to receive a high voltage signal and a supply voltage, and output the modulation voltage to the modulation input terminal. The feedback circuit is used to adjust the modulation voltage according to a difference between the supply voltage and a reference voltage. The energy storage circuit is charged by the charging current to pull up the supply voltage.
Power amplifier circuit
A power amplifier circuit amplifies a radio-frequency signal in a transmit frequency band. The power amplifier circuit includes an amplifier, a bias circuit, and an impedance circuit. The amplifier amplifies power of a radio-frequency signal and outputs an amplified signal. The impedance circuit is connected between a signal input terminal of the amplifier and a bias-current output terminal of the bias circuit and has frequency characteristics in which attenuation is obtained in the transmit frequency band. The impedance circuit includes first and second impedance circuits. The first impedance circuit is connected to the signal input terminal. The second impedance circuit is connected between the first impedance circuit and the bias-current output terminal.
BALANCED RADIO FREQUENCY POWER AMPLIFIER, CHIP AND COMMUNICATION TERMINAL
Disclosed in the present invention are a balanced radio frequency power amplifier, a chip and a communication terminal. The radio frequency power amplifier divides, by means of a 90-degree power splitter unit, a radio frequency input signal into two equal-amplitude signals having a phase difference of 90 degrees, the two radio frequency input signals are amplified and then inputted into an adjustable 90-degree power combiner, and the values of a adjustable capacitor and an adjustable resistor in the adjustable 90-degree power combiner are controlled by means of a control unit, so as to synthesize the two radio frequency input signals into one radio frequency input signal when the phase difference and amplitude difference of the two signals at different frequencies are the smallest, and to input the radio frequency input signal into a circuit of the next stage by means of a specific radio frequency transmission path.
POWER AMPLIFIER CIRCUIT, POWER AMPLIFIER DEVICE, AND RF CIRCUIT MODULE
A power amplifier circuit includes an amplifier transistor which amplifies a radio frequency signal applied to its base and outputs the amplified signal; a resistance element having a first end, and a second end electrically connected to the base of the amplifier transistor; a first bias transistor having a collector to which a first voltage is applied, a base to which a first bias voltage is applied, and an emitter electrically connected to the first end of the resistance element and which supplies a bias current to the base of the amplifier transistor through the resistance element; and a second bias transistor having an emitter electrically connected to the emitter of the first bias transistor and the first end of the resistance element, a base to which a second bias voltage is applied, and a collector to which a second voltage lower than the first voltage is applied.