An amplifier includes an amplifying device and a bias circuit for providing a bias voltage for the amplifying device. The bias circuit is configured to provide the bias voltage in dependence of an output signal of an optical coupling arrangement which provides for electrical isolation.

A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

A power amplifier circuit includes a Doherty amplifier including a divider that divides a first signal into a second signal and a third signal, a carrier amplifier that amplifies the second signal and outputs a fourth signal, a peak amplifier that amplifies the third signal and outputs a fifth signal, a combiner that combines the fourth signal and the fifth signal and outputs an amplified signal of the first signal, a first bias circuit that supplies a first bias current or voltage to the carrier amplifier, and a second bias circuit that supplies a second bias current or voltage corresponding to a control signal to the peak amplifier; and a control circuit that supplies the control signal corresponding to a level of the second signal to the second bias circuit. The control circuit includes a detecting unit, an output unit, and a filter circuit.

Aspects of this disclosure relate to an adaptive biasing circuit for a power amplifier. The adaptive biasing circuit can include a shunt resistor arrangement and/or a floating gate linearizer arrangement.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.

Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

A current mirror circuit connectible to an amplifier circuit to set a bias point thereof includes a current mirror circuit, and a bias resistor connected thereto. The bias resistor is connectible to the amplifier circuit. A first helper circuit is connected in parallel with the bias resistor, and is selectively activated for a first predetermined duration by a first control signal. The activated first helper circuit defines a lower resistance path relative to the bias resistor to shorten a rising transient response of the amplifier circuit as the current mirror circuit is activated.

In a general aspect, a circuit can include an amplifier circuit including a first amplifier, a first feedback path, and a second feedback path. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier. The circuit can also include a loop circuit including a second amplifier. The loop circuit can be configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and into the negative input of the first amplifier.