The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal. The compensation differential signal is applied to the output terminals of the first and second capacitors via a pair of resistors, respectively.

An amplifier and a method of outputting a waveform of a music signal capable of outputting a waveform of a music signal exceeding a power supply voltage is provided. An amplifier includes a power supply, an input terminal for a music signal, an amplifying circuit which amplifies the music signal using the power supply, and a jumping-up circuit which is connected to an output end of the amplifying circuit and outputs a waveform exceeding a voltage value of the power supply.

A current reuse FET amplifier according to the present invention provides an effect of reducing a variation of bias current of the amplifier, with gate voltage or a resistor for self-biasing of an FET of the amplifier changing in accordance with a process variation of saturation current Idss of the FET.

An amplifying circuit is provided. The amplifying circuit includes a bias circuit receiving an operating voltage from a power supply circuit and generating a first bias voltage, a resistance circuit connected between the bias circuit and a gate node and transferring the first bias voltage to the gate node, a start-up circuit generating a high-level start-up voltage and supplying the start-up voltage to the gate node before the operating voltage is supplied, based on a control signal, and an amplifier started-up by receiving the start-up voltage and then receiving the operating voltage and the first bias voltage to amplify a high frequency signal input through the gate node.

An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.

Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.