A radio-frequency power converter and a radio-frequency transmission system for magnetic resonance imaging are provided in embodiments of the present invention. The radio-frequency power converter comprises a printed circuit board, the printed circuit board comprises a first circuit layer, a ground layer, and one or a plurality of intermediate layers located between the first circuit layer and the ground layer. A plurality of planar spiral inductors connected in parallel are formed on the first circuit layer. One ends of the plurality of inductors are connected to each other and respectively connected to one end of a first capacitor, the other ends of the plurality of inductors are respectively connected to one ends of a plurality of second capacitors, and the other ends of the plurality of second capacitors are all grounded.

An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2ϕ degrees (45<ϕ<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about ϕ degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about ϕ degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

A wideband amplifier includes an input matching network for matching a transconductor stage to an input impedance and includes an output matching network for matching the transconductor stage to an output impedance. Both the input and output matching networks each includes a parallel LC tank circuit arranged in parallel with a series LC tank circuit. The tank circuit arrangements configure the input and output matching networks to be resonant at a first frequency, a midrange frequency that is greater than the first frequency, and a second frequency that is greater than the midrange frequency to provide wideband matching.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x≈1.5).

A low noise amplifier includes a transistor that amplifies and outputs inputted signals, a buffer that propagates outputs of the transistor to a subsequent circuit, a variable current source that supplies a bias current to the transistor, and a variable resistor connected between a gate terminal of the transistor and a terminal of the transistor to which the variable current source is connected, wherein in a case in which the inputted signals do not pass through the low noise amplifier, the buffer blocks outputs of the transistor, and settings of the variable current source and the variable resistor differ from settings in a case in which the inputted signals pass through the low noise amplifier.

A radio frequency circuit includes a first acoustic wave filter that is connected to a common terminal and includes a first acoustic wave resonator, a first LC filter that is connected to the common terminal via the first acoustic wave filter and includes at least one of an inductor or a capacitor, a second acoustic wave filter that is connected to the common terminal and includes a second acoustic wave resonator, and a second LC filter that is connected to the common terminal via the second acoustic wave filter and includes at least one of an inductor or a capacitor.

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.