Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal.

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

An envelope stacking power amplifier system reduces current for a given output power level without sacrificing the ability to support large voltage swings at saturation and therefore increases efficiency at the maximum linear operating power and all power levels below that. The system includes a stack/unstack controller including circuitry configured to switch the RF power amplifier system between a stacked mode in which first and second RF amplifiers are coupled in a stacked configuration and an unstacked mode in which the first and second RF amplifiers are coupled in an unstacked configuration in response to one or more mode-control signals, the stacked configuration providing reduced current compared to the unstacked configuration.

A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

A method for biasing a power amplifier using a transmission signal having a time-varying envelope is provided. The method comprises producing a time-varying signal indicative of an amplitude of the envelope of the transmission signal and comparing the time-varying signal to a plurality of distinct threshold voltages. The method further comprises, for each of the plurality of distinct threshold voltages exceeded by the time-varying signal, providing a respective bias voltage to a respective input of a summing device and producing, using the summing device, an output bias voltage that is at least a sum of the respective bias voltages provided to the respective inputs of the summing device. The method further comprises biasing the power amplifier with the output bias voltage and amplifying the transmission signal using the power amplifier biased at the output bias voltage.

A semiconductor devices comprises a first member including a first circuit partially formed by an elemental semiconductor element at a surface layer, a first conductive raised portion at the first member, and a second member smaller than the first member in plan view joined to the first member. The second member includes a second circuit partially formed by a compound semiconductor element. A second conductive raised portion is at the second member. A power amplifier includes a first-stage amplifier circuit included in the first or second circuit and a second-stage amplifier circuit included in the second circuit. The first circuit includes a first switch for inputting to the first-stage amplifier circuit a radio-frequency signal inputted to a selected contact, a control circuit to control the first- and second-stage amplifier circuits, and a second switch for outputting from a selected contact a radio-frequency signal outputted by the second-stage amplifier circuit.

The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.