A signal booster is disclosed that includes a first interface port, a second interface port, a third interface port, a downlink signal splitter device, an uplink signal splitter device, a main booster and a front-end booster. The uplink signal splitter device can include a first uplink splitter port configured to direct uplink signals from the second interface port towards the first interface port. The uplink signal splitter device can include a second uplink splitter port configured to direct uplink signals from the third interface port towards the first interface port. The main booster can include a main downlink amplification path and a main uplink amplification path. The front-end booster can include a front-end downlink amplification path and a front-end uplink amplification path.

A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an impedance change by the first impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the input terminal, and prevents an impedance change by the second impedance adjustment circuit with respect to the frequency of the fundamental component at the input terminal; and a second frequency separation circuit which prevents an impedance change by the third impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the output terminal, and prevents an impedance change by the fourth impedance adjustment circuit with respect to the frequency of the fundamental component at the output terminal.

Included is a compensation circuit having one end connected to another end of a first output circuit and another end of a second output circuit and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

A bandpass parametric amplifier circuit includes a plurality of unit cells. At least one unit cell includes a first inductor having a first node coupled to a center conductor and a second node coupled to ground. There is a first capacitor having a first node coupled to the center conductor and a second node coupled to ground. There is a second inductor having a first node coupled to the center conductor. A second capacitor has a first node coupled to a second node of the second inductor. The second capacitor and the second inductor are in series with the center conductor.

A radio frequency module includes: a first low-noise amplifier including a first amplification element as an input stage and a second amplification element as an output stage; a second low-noise amplifier including a third amplification element as an input stage and the second amplification element as an output stage, the third amplification element being different from the first amplification element; a first matching circuit connected to an input terminal of the first low-noise amplifier; and a module substrate including a first principal surface and a second principal surface opposite to each other, wherein the first amplification element is disposed on one of the first principal surface and the second principal surface, and the first matching circuit is disposed on the other of the first principal surface and the second principal surface.

A high frequency amplifier 1 includes an input terminal P.sub.IN, an output terminal P.sub.OUT, a transistor 5 configured to amplify an RF signal applied to the input terminal P.sub.IN, a matching circuit 9 for a fundamental of the RF signal and a reflection circuit 7 for a harmonic relative to the fundamental, the matching circuit 9 and the reflection circuit 7 being connected in series between the transistor 5 and the output terminal P.sub.OUT, an extraction circuit 13 configured to extract a harmonic appearing at the output terminal P.sub.OUT, processing circuits 15, 17 configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit 13, and a multiplexing circuit 19 configured to multiplex the harmonic processed by the processing circuits 15, 17 to the harmonic reflected by the reflection circuit 7 and give the multiplexed harmonic to the transistor 5.

A plurality of transmission lines (3b,3c) are connected to a transistor (1) and have different characteristic impedances. A plurality of open stubs (4a,4b) are connected to the plurality of transmission lines (3b,3c) respectively. A length of each open stub (4a,4b) is shorter than a length of each transmission line (3b,3c).

An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal.

A monolithic microwave integrate circuit (MMIC) presents as a power amplifier including a 9:1 overlay transformer and artificial low impedance transmission lines. The 9:1 overlay transformer effects the output impedance thereof. The artificial low impedance transmission lines behave as inductors without occupying an amount of space equivalent to that of an inductor having similar properties as the artificial low impedance transmission line.

A differential power amplifier includes an input matching network, a first-stage amplification circuit, a first inter-stage matching network, a second-stage amplification circuit, a second inter-stage matching network, a third-stage amplification circuit, and an output matching network. The first-stage amplification circuit and the second-stage amplification circuit are single-ended input single-ended output circuits. The third-stage amplification circuit is a dual input dual output circuit. The second inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The output matching network includes a second transformer T2. The inter-stage matching networks and the output matching network are realized by the first transformer T1 and the second transformer T2, which reduces an inter-stage matching difficulty, optimizes input return loss and gain, and improves output power.