A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.

This application relates to audio driving circuits having good audio performance. The circuit (301) has a forward signal path between an input (103) for receiving an input audio signal (S.sub.IN) and an output (104) for outputting an output signal (S.sub.OUT) with an amplifier module (102) in the forward signal path. An error block (302) is arranged to receive a first signal (S.sub.FF) derived from the input signal and also a second signal (S.sub.FB) derived from the output signal and determine a first error signal (.sub.1) indicative of a difference between the first and second signals. A first processing module (204) is operable to generate a compensation signal (S.sub.C) to be applied to the input signal (S.sub.IN) upstream of the amplifier module (102) based on the first error signal. The error block (302) comprises a second processing module (303/303a) configured to apply a linear transfer function to one of the first signal or the second signals prior to determining the first error signal. In some embodiments the second processing module may apply a linear transfer function which is adaptive based on a second error signal (.sub.2) indicative of the error between the first and second signals after the linear transfer function has been applied.

A digital amplifier includes a pulse-width adjustment circuit that adjusts the pulse width of a digital signal, a switching circuit that amplifies the output signal of the pulse-width adjustment circuit, and a feedback signal generator that generates a feedback signal based on the output signal of the switching circuit.

A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.

An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.

Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled.

An analog discrete current mode negative feedback amplifier circuit for use with a micro-fused strain gauge is disclosed. The amplifier circuit includes a Wheatstone bridge coupled to a first power supply and a second power supply. The first power supply and the second power supply can be configured such that the periodically alternate between two voltage levels. The Wheatstone bridge can be coupled to a negative feedback amplifier circuit with common mode detection. The amplifier circuit can comprise a differential amplifier with a negative feedback configuration coupled to a common mode amplifier. In addition, the output of each of the amplifiers can be coupled to a common-mode amplifier. In a pressure sensing application, the output of the common mode amplifier serves to output the temperature while the differential amplifiers serve to output the pressure.

Aspects disclosed herein eliminate audible disturbances that may occur when an audio amplifier is activated and deactivated. A feedback circuit is used to maintain a closed loop when transistors of a power output stage are activate or deactivated, thereby enabling the charge to build or dissipate without causing an audible disturbance. Further, in certain implementations, the power output stage may remain in an enable state for a period of time after deactivation of the audio amplifier regardless of whether an audio input signal is received enabling dissipation of charge without causing an audible disturbance.

Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled.

A circuit includes a plurality of first stage integrators. Each of the plurality of first stage integrators includes a first input, a second input, a third input and an output. The first input of each of the plurality of first stage integrators is coupled to a different one of circuit inputs, the second input is coupled to a first reference input, the third input is coupled to a second reference input and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator. The circuit includes a second stage integrator which includes a first input coupled to each of the first inputs of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator.