A carrier aggregation method can include amplifying a first signal with a first current converter to generate a current representative of the amplified first signal, and amplifying a second signal with a second current converter to generate a current representative of the amplified second signal. The method can further include processing the amplified first signal and the amplified second signal with an adder circuit, with the first current converter and the adder circuit forming a first cascode amplifier, and the second current converter and the adder circuit forming a second cascode amplifier. The method can further include providing an output signal at a common output node that is coupled to an output of each of the first and second cascode amplifiers.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Provided is an electronic device that includes a communication processor; a transceiver electrically connected to the communication processor; a first power amplifier electrically connected to the transceiver; a first antenna electrically connected to the first power amplifier; and a first supply adjustor electrically connected to the communication processor and the first power amplifier. The communication processor can be set to perform a first determination about whether a carrier bandwidth part of a first signal transmitted through the first antenna exceeds a first threshold value, perform a second determination about whether the power of the first signal exceeds a second threshold value, select a first tracking mode as an envelope tracking mode or an average power tracking mode on the basis of at least a portion of the first determination and the second determination, and control the first supply adjustor using the selected first tracking mode.

Apparatus and methods for power detection with enhanced dynamic range are provided. In certain embodiments, a front end system includes a power amplifier that amplifies a radio frequency (RF) input signal to generate an RF output signal, a directional coupler that generates a sensed RF signal based on sensing the RF output signal from the power amplifier, and a power detector that processes the sensed RF signal to generate a detection signal indicating an output power of the power amplifier. Additionally, the power detector includes two or more detection paths providing different amounts of gain to the sensed RF signal from the directional coupler.

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.

A high-frequency circuit includes a power amplifier for a communication band A, and a power amplifier for a communication band B. Transmission in the communication band A, transmission in the communication band B, and reception in the communication band C can be simultaneously used. A frequency range of intermodulation distortion generated between a second harmonic wave of a transmission signal of the communication band A and a fundamental wave of a transmission signal of the communication band B, overlaps with at least part of a reception band of the communication band C. The power amplifier includes amplifying elements and an output trans including coils. One end of the coil is connected with an output of the amplifying element, the other end of the coil is connected with an output of the amplifying element, and one end of the coil is connected with an output terminal of the power amplifier.

A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.

An electronic device includes: an antenna, a PAM including a PA configured to amplify a transmitting signal and a protection circuit, a PMIC configured to supply voltage to the PA, and at least one processor is configured to: provide a first signal, to a NAND gate in the protection circuit, provide to a AND gate in the protection circuit, a second signal indicating a result of a logical operation between the first signal and a bias enable signal for the PA, provide to the AND gate, a third signal indicating whether the transmitting signal is input to the PAM, provide to a switching circuit, a fourth signal indicating a result of logical operation between the second signal and the third signal, identify whether to apply a bias voltage to the PA based on the fourth signal, and transmit the transmitting signal, to the external electronic device, via the antenna.

An amplifier includes a first amplification circuit, a second amplification circuit including first and second amplification transistors controlled by the first amplification circuit to generate first and second output signals and a bias transistor turned on based on a bias signal to generate the first output signal, a filter circuit including a bias capacitor connected to the first amplification transistor and the bias transistor to generate the first bias signal using a first bias voltage, and a feedback circuit configured to receive the first and second output signals and output a feedback signal that adjusts an average of the first and second output signals to correspond to a reference signal, to the first amplifier. The filter circuit adjusts a voltage of the bias capacitor such that a voltage of the bias capacitor when the amplifier is disabled corresponds to a voltage of the bias capacitor when the amplifier is enabled.