Patent classifications
H03F2200/294
LOW NOISE AMPLIFIER AND OPERATING METHOD THEREOF
A low noise amplifier is provided. The low noise amplifier includes a first transistor that receives a radio frequency (RF) signal through a control terminal, a second transistor that forms a cascode structure together with the first transistor, and receives an output signal of the first transistor through a first terminal, and a third transistor that forms a cascode structure together with the second transistor, and receives an output signal of the second transistor through the first terminal. The first to third transistors perform an amplification operation in response to application of a first power source voltage, and the first and second transistors or the first and third transistors perform an amplification operation in response to application of a second power source voltage.
Multi-mode WiFi bluetooth RF front-ends
A radio frequency front end circuit for a multimode transceiver has a first operating mode transmit input port, a second operating mode transmit input/receive output port, and a hybrid first and second operating mode receive output port. A first switch network has one or more switch elements together selectively connecting the first operating mode transmit input port, the second operating mode transmit input/receive output port, and the hybrid first and second operating mode receive output port to a coexistence filter first port. A second switch network has one or more switch elements that together selectively connect a coexistence filter second port to an antenna port.
Front end module (FEM) with integrated functionality
A front end radio frequency (RF) module including one or more first filter circuits configured to implement a front end function by filtering first signals communicated between one or more first antenna and a transceiver and one or more second filter circuits configured to implement at least a portion of an additional network function within the front end RF module by filtering second signals communicated between one or more second antennas and the transceiver.
Duplexer with balanced impedance ladder
An electrical balance duplexer has multiple impedance gradients and multiple impedance tuners. The electrical balance duplexer transmits an outgoing signal from a transmitter during a transmission mode when a first set of impedance gradients of the multiple impedance gradients is operating in a first impedance state and a first set of impedance tuners of the multiple impedance tuners is operating in a second state. The electrical balance duplexer isolates the outgoing signal from a receiver during the transmission mode when a second set of impedance gradients of the multiple impedance gradients and a second set of impedance tuners of the multiple impedance tuners are operating in the second impedance state.
Wideband distributed power amplifiers and systems and methods thereof
A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.
Amplifier with built in time gain compensation for ultrasound applications
An ultrasound circuit comprising a trans-impedance amplifier (TIA) with built-in time gain compensation functionality is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA is, in some cases, followed by further analog and digital processing circuitry.
Receiver circuits with blocker attenuating rf filter
A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.
Cable loss compensation system for time domain duplexed (TDD) radios using embedded radio frequency (RF) control
Technologies directed to cable-loss compensation are described. An apparatus includes a triplexer, a front-end module (FEM) circuit, and a control circuit. The triplexer is coupled to a radio frequency (RF) cable. The triplexer receives a first RF signal and a DC power signal from a device via the RF cable and sends a detection signal being indicative of a transmit power level of the first RF signal to the device via the RF cable. The transmit power level includes an insertion loss of the RF cable. The FEM circuit is coupled to the triplexer and includes a power amplifier (PA). The control circuit is coupled to the triplexer and measures the transmit power level of the first RF signal and converts the first RF signal into the detection signal. The control circuit sends the detection signal back to the device via the RF cable and enables the PA.
TRANSFER PRINTING FOR RF APPLICATIONS
A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.
MONOLITHIC MICROWAVE INTEGRATED CIRCUITS TOLERANT TO ELECTRICAL OVERSTRESS
Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.