Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.

An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a mixer that outputs signals to a transimpedance amplifier. The mixer has an output impedance that varies depending on the frequency of operation. An adjustable resistance can be coupled to the input of the transimpedance amplifier. A control circuit can tune the adjustable resistance to compensate for changes in the output impedance of the mixer as the transceiver operates across a wide range of frequencies.

A radio frequency module includes: a first low-noise amplifier including a first amplification element as an input stage and a second amplification element as an output stage; a second low-noise amplifier including a third amplification element as an input stage and the second amplification element as an output stage, the third amplification element being different from the first amplification element; a first matching circuit connected to an input terminal of the first low-noise amplifier; and a module substrate including a first principal surface and a second principal surface opposite to each other, wherein the first amplification element is disposed on one of the first principal surface and the second principal surface, and the first matching circuit is disposed on the other of the first principal surface and the second principal surface.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.

A low noise amplifier includes a plurality of serially-coupled amplifier stages. Each serially-coupled amplifier stage provides a respective amplified signal, wherein a first amplifier stage receives an input signal, and a last amplifier stage provides an amplified output signal. Each serially-coupled amplifier stage includes a single-ended amplifier having an input, and an output providing the respective amplified signal, a first passive network, and a second passive network. The first passive network has a first terminal forming an input of a respective one of said plurality of serially-coupled amplifier stages, and a second terminal coupled to said input of said single-ended amplifier, the first passive network including a first capacitor coupled in series between the first and said second terminals of the first passive network. The second passive network is coupled in parallel to the single-ended amplifier and between the input and the output of the single-ended amplifier.

A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.

A method of determining filter coefficients of an equalizer circuit for equalizing a non-linear electronic system is described. The equalizer circuit includes a Volterra filter circuit. Further, an equalizer circuit for equalizing a non-linear electronic system and an electronic device are described.