Patent classifications
H03F2200/301
Amplification circuit
Provided is an amplification circuit that amplifies an input signal and outputs an amplified signal. The amplification circuit includes: an amplification element that outputs the amplified signal from an output terminal thereof; an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element; a variable resistor that is connected in parallel with the inductor; and a resistance value adjusting circuit that adjusts a resistance value of the variable resistor in accordance with the temperature.
Parallel tuned amplifiers
The disclosed technology provides a system for transmitting wireless power for charging electronic devices, e.g., smartphones, medical appliances, industrial equipment, and robotics. Some embodiments include parallel tuned resonant LC networks, load networks, and impedance matching networks for Class D and E, single-ended or differential, amplifier topologies for wireless power transfer in resonant inductive systems.
DEVICE HAVING A COUPLED INTERSTAGE TRANSFORMER AND PROCESS IMPLEMENTING THE SAME
A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.
MATRIX POWER AMPLIFIER
A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.
FULLY INTEGRATED LOW-NOISE AMPLIFIER
A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
Process of using a submerged combustion melter to produce hollow glass fiber or solid glass fiber having entrained bubbles, and burners and systems to make such fibers
Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.
LNA with programmable linearity
A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
LNA with Programmable Linearity
A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
Cascode Amplifier Bias Circuits
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
Phase-switched impedance modulation amplifier
Described is a phase-switched phase-switched, impedance modulation amplifier (PSIM). The PSIM has an input that can be coupled to a source and an output that can be coupled to a load. The PSIM includes one or more phase-switched reactive elements and a controller. The controller provides a control signal to each of the one or more phase-switched reactive elements. In response to one or more control signals provided thereto, each phase-switched reactive element provides a corresponding selected reactance value such that an impedance presented to an input or output port of an RF amplifier may be varied.