A power amplifier circuit includes an amplifier transistor which amplifies a radio frequency signal applied to its base and outputs the amplified signal; a resistance element having a first end, and a second end electrically connected to the base of the amplifier transistor; a first bias transistor having a collector to which a first voltage is applied, a base to which a first bias voltage is applied, and an emitter electrically connected to the first end of the resistance element and which supplies a bias current to the base of the amplifier transistor through the resistance element; and a second bias transistor having an emitter electrically connected to the emitter of the first bias transistor and the first end of the resistance element, a base to which a second bias voltage is applied, and a collector to which a second voltage lower than the first voltage is applied.

An apparatus is disclosed for implementing a clamping circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled thereto. The clamping circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.

A low-noise amplifier (LNA) includes a first transistor, a first source inductor coupled to a source of the first transistor, and a second transistor, wherein a source of the second transistor is coupled to a drain of the first transistor, a gate of the second transistor is coupled to a bias circuit, and a drain of the second transistor is coupled to an output of the LNA. The LNA also includes an output inductor coupled between a supply rail and the output of the LNA, wherein the output inductor is magnetically coupled with the first source inductor.

An apparatus is disclosed for implementing a Darlington circuit with a driver amplifier to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, a power amplifier, and a Darlington circuit. The driver amplifier includes a driver amplifier output and a transistor, with the driver amplifier coupled between the input port and the output port. The power amplifier includes a power amplifier input, and the power amplifier is coupled between the driver amplifier output and the output port. The Darlington circuit is coupled to the driver amplifier via a node that is coupled between the input port and the power amplifier input.

An apparatus is disclosed for implementing a Darlington circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a Darlington circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The Darlington circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A transimpedance amplifier (TIA) for converting an input current at an input node into an output voltage at an output node, the TIA comprising: a first amplifier stage having a first input coupled to the input node and a first output; a feedback path between the first output and the first input; a second amplifier stage in the feedback path having a second input, the second input coupled to the first output of the first amplifier stage; a feedback resistor in the feedback path coupled between an output of the second amplifier stage and first input of the first amplifier stage; and an output stage, comprising: a load resistor coupled between a reference voltage node and a T-coil, the T-coil comprising first and second inductors coupled in series at an inductor node, the T-coil coupled between the first output and the load resistor, the inductor node coupled to the output node of the TIA.

A Doherty amplifier for amplifying an input signal to an output signal, the Doherty amplifier comprising: a main amplifier for receiving a first signal and for amplifying the first signal to generate a first amplified signal; a first peak amplifier for receiving a second signal and for generating a second amplified signal, the first peak amplifier only operating when the second signal has reached a first threshold power, the first and second signal split from the input signal; and output circuitry to combine the first and second amplified signals to generate an output signal having an operating bandwidth, the output circuitry comprising inductors arranged in the format of a branch line coupler, the inductors coupled to the output parasitic capacitances of the main and peak amplifier.

Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node.

Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.