A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

In certain aspects, an amplifier includes a first transistor including a gate, a drain, and a source, wherein the gate of the first transistor is coupled to a first input of the amplifier. The amplifier also includes a second transistor including a gate, a drain, and a source, wherein the gate of the second transistor is coupled to a second input of the amplifier. The amplifier further includes a first signal path coupled between the first input of the amplifier and the source of the second transistor, a second signal path coupled between the second input of the amplifier and the source of the first transistor, a first load coupled to the drain of the first transistor, and a second load coupled to the drain of the second transistor.

The present invention relates to an amplification device (10) of an input signal comprising: a first amplification stage (12), a second amplification stage (14), each amplification stage (12, 14) comprising: a switching circuit (22), the switching circuit (22) being able to generate, as output (22A, 22B), a switched signal having at least two states, and an inductive element (24) able to smooth the switched signal to obtain a smoothed signal (I1, I3), the smoothed signal (I1, I3) having a useful component and a stray component. The amplification device (10) further comprises a compensation circuit (16), for each amplification stage (12, 14), able to generate a compensation signal (I2, I4) of the stray component of the smoothed signal (I1, I3) generated in the inductive element (24) of the corresponding amplification stage (12, 14).

Various buck-boost amplifier architectures are disclosed. In some architectures, a plurality of amplifiers use one or more inductors from a shared bank of inductors as needed to deliver variable amounts of power to respective loads. In some architectures, each amplifier includes multiple inductors and switches that are controlled to vary the number of inductors used in an amplifier based on a power requirement of the amplifier to drive its load. In some architectures, the switches include well switching devices. In some architectures, each amplifier drives multiple loads and is operated in a single inductor multiple output (SIMO) mode. In all architectures, the loads include speakers, piezo elements, and motors.

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

A gradient amplifier driver stage circuit includes: a gradient coil and a plurality of gradient driver modules electrically cascaded with each other and forming an output end, the output end being electrically connected to the gradient coil, wherein each gradient driver module includes a pre-stage power supply and a bridge amplifier connected in parallel, output voltage of the pre-stage power supplies of the plurality of gradient driver modules are the same, and each gradient driver module is configured to provide an inductive voltage drop and a resistive voltage drop on the gradient coil.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.