Apparatus and methods for power amplifier bias modulation for low bandwidth envelope tracking are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier that amplifies an RF signal and a low bandwidth envelope tracker that generates a power amplifier supply voltage for the power amplifier based on an envelope of the RF signal. The envelope tracking system further includes a bias modulation circuit that modulates a bias signal of the power amplifier based on a voltage level of the power amplifier supply voltage.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.