The present disclosure relates to an integrated wideband Radio Frequency (RF) amplifier, based on a complementary metal oxide semiconductor (CMOS) technology. In an embodiment the amplifier addresses the shortcomings of conventional wideband amplifiers and is based on a distributed amplifier (DA) topology which typically exhibit severe performance degradation when externally loaded with parasitic circuit elements. In an embodiment of the present invention a buffer amplifier at the output of a conventional DA is able to compensate the impact of parasitic elements. The disclosed circuit can be implemented by fabricating the wideband RF amplifier integrated circuit (IC) on a 130 nm CMOS technology or other comparable CMOS technologies.

High efficiency transmit-receive switches in accordance with embodiments of the invention are disclosed. In one embodiment, a high efficiency transmit receive switch includes a power input coupled to a power supply, an amplifier output port and a transmit switch input port coupled to a circulator, a received signal circuit port coupled to a first PIN diode coupled to a second PIN diode via a first transmission line and spaced a fractional wavelength apart, the transmit switch input port is coupled to a third PIN diode coupled to a harmonic filter, a second transmission line coupled between the second PIN diode and to the third PIN diode, spaced a fractional wavelength apart, the transmit circuit signal port is coupled to an amplifier, the amplifier is coupled to the amplifier output port, the second transmission line is coupled to the bias current generator coupled to the output port.

An amplifier circuit (200) for compensating an output signal provided at an output (212) of a circuit (210) is disclosed. The amplifier circuit (200) comprises an output transmission line (230) connected between the output (212) of the circuit (210) and an output port (240) and an amplifier (220). The amplifier (220) comprises multiple sub-amplifiers (221, 222, 223, 224), inputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled to an input transmission line (250) for receiving an error signal; and outputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled at respective places along the output transmission line (230) to inject a compensation signal to the output port (240). The error signal is derived from a reference input signal and the output signal of the circuit (210), and is amplified in the amplifier (220) into the compensation signal.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A Doherty power amplifier that includes an input, an output, a main power amplification device connected between the input and the output; and an auxiliary power amplification device connected between the input and the output. The auxiliary power amplification device is arranged in parallel with the main power amplification device. The Doherty power amplifier further includes a first dual-mode impedance transformer connected between the main power amplification device and the output, and a second dual-mode impedance transformer between the auxiliary power amplification device and the output. The first and second dual-mode ITs each is adapted to convert an input impedance of a corresponding one of the main and auxiliary power amplification devices to a load impedance at the output, at two frequencies simultaneously.

A distributed amplifier includes: an input-side transmission line; M amplification circuits; M output-side transmission lines; and a combination circuit configured to combine outputs of the M output-side transmission lines; wherein the input-side transmission line has an input-side serial line formed by connecting in series MN unit transmission lines each including the same line length, and an input-side terminating resistor, the M amplification circuits each includes N amplifiers and the N amplifiers of the i-th amplification circuit take the input node of the ((k1) M+i)-th input-side transmission line to be the input, and the output-side transmission line includes an output-side serial line including N transmission lines each being connected in series between the neighboring outputs of the N amplifiers and each having a line width in which the phase of the output of the amplifier in each stage agrees with one another.

A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are disposed on opposite sides of the active region.

An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier.