A packaged RF amplifier device includes input and output leads and a transistor die. The transistor die includes a transistor with a drain-source capacitance below 0.1 picofarads per watt. The device also includes a conductive connection between the transistor output terminal and the output lead, and a baseband termination circuit between the transistor output terminal and a ground reference node. The baseband termination circuit presents a low impedance to signal energy at envelope frequencies and a high impedance to signal energy at RF frequencies. The baseband termination circuit includes an inductive element, a resistor, and a capacitor connected in series between the transistor output terminal and the ground reference node. Except for a minimal impedance transformation associated with the conductive connection, the device is unmatched between the transistor output terminal and the output lead by being devoid of impedance matching circuitry between the transistor output terminal and the output lead.

A power amplifier circuit includes: a high pass filter that has one end into which a high frequency input signal is inputted; a first amplifier that amplifies the high frequency input signal outputted from the other end of the high pass filter and outputs a high frequency signal obtained through the first amplification; a second amplifier that amplifies the high frequency signal and outputs a high frequency output signal obtained through the second amplification; an automatic transformer that performs impedance matching between the first amplifier and the second amplifier; and an impedance circuit, one end of which is electrically connected with the other end of the high pass filter, the other end of which is electrically connected with an output terminal of a bias circuit outputting bias voltage or bias current to the first amplifier, and that outputs the high frequency input signal to the bias circuit.

Power amplifier apparatuses and techniques for optimizing the design of power amplifiers are disclosed. In one aspect, a method for optimizing a power amplifier includes selecting a circuit topology for the power amplifier. The circuit topology includes one or more photoconductive switches and an impedance matching network including one or more parameter values representative of the impedance matching network or the photoconductive switches that can be adjusted. The method further includes selecting one or more optimization goals for the impedance matching network and the one or more photoconductive switches, and adjusting the one or more parameter values according to the one or more optimization goals. The one or more optimization goals include an efficiency at a particular power output.

A power amplifier circuit includes a first amplifier circuit configured to amplify a first signal of a first frequency band and output a first amplified signal having a first power, a second amplifier circuit configured to amplify a second signal of the first frequency band or a second frequency band different from the first frequency band and output a second amplified signal having a second power different from the first power, and a first variable adjustment circuit disposed between the second amplifier circuit and a first circuit subsequent to the second amplifier circuit, the first variable adjustment circuit being configured to be capable of adjusting a first impedance of the first circuit seen from the second amplifier circuit.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A power amplifier circuit includes a first amplification path including a first power amplifier, a second amplification path including a second power amplifier, a first switching circuit configured to electrically connect either the first amplification path or the second amplification path and a first output terminal to each other, a second switching circuit configured to electrically connect an input terminal and any one of a plurality of second output terminals to each other, and a matching circuit configured to electrically connect the first output terminal and the input terminal to each other and achieve impedance matching between the first output terminal and the input terminal.

A power amplifying circuit includes a first amplifying unit that amplifies a first radio-frequency signal and a second amplifying unit that amplifies a second radio-frequency signal. The first amplifying unit includes a first matching circuit that performs impedance matching for a circuit in a preceding stage, and a first amplifying circuit that amplifies the first radio-frequency signal that has passed through the first matching circuit. The second amplifying unit includes a second matching circuit that performs impedance matching for the circuit in the preceding stage, a resistor including a first end and a second end, the first end being electrically connected to the second matching circuit, and a second amplifying circuit that is electrically connected to the second end of the resistor and that amplifies the second radio-frequency signal that has passed through the resistor.

A power amplifier circuit includes a power amplification circuit and a diode assembly. The diode assembly is connected in series with a transistor amplification circuit of the power amplification circuit, and the transistor amplification circuit is configured to, when load of power amplifier is mismatched, turn the diode assembly on, so as to divide current voltage to at least two electrodes of the transistor amplification circuit.

A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.