An architecture of radio frequency front-end includes a power amplifier module integrated duplexer (PAMiD), an antenna and at least one tunable matching network; herein, the PAMiD includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna, and is configured to adjust the impedance of the output end of the power amplifier and/or the impedance of the input end of the antenna.

An electronic device may include wireless circuitry having one or more radio-frequency amplifiers coupled to differential coupled lines. The differential coupled lines may provide routing and impedance matching for the radio-frequency amplifiers with minimal power loss. The differential coupled lines may include a first pair of coupled lines and a second pair of coupled lines. The first pair of coupled lines may include a first conductive routing path coupled to a first voltage line and a second conductive routing path routed along the first conductive routing path and coupled to a second voltage line. The second pair of coupled lines may include a third conductive routing path coupled to the first voltage line and a fourth conductive routing path routed along the third conductive routing path and coupled to the second voltage line.

An embodiment differential amplifier circuit includes an amplifier section including differential pair transistors to which a differential signal is input and a tail current circuit made up of a short stub provided between a ground terminal of the amplifier section and a ground. In an embodiment, an electrical length of the short stub is shorter than a quarter wavelength of an operation frequency of the differential amplifier circuit.

A bias circuit includes: a first transistor having an emitter or a source which supplies a bias to an amplifier operating by a power source voltage through a first resistive element and a base or a gate; a first capacitor having a first end electrically connected to the base or the gate of the first transistor and a second end connected to a ground; and a second transistor having a collector or a drain electrically connected to the base or the gate of the first transistor, a base or a gate electrically connected to the base or the gate of the first transistor, and an emitter or a source connected to a node which is supplied with a signal with experience of being amplified by the amplifier and the power source voltage.

Apparatus and methods for biasing power amplifiers are provided herein. In certain embodiments, a power amplifier includes a bipolar transistor having a base biased by a bias network having a reactance that controls an impedance at the transistor base to achieve substantially flat phase response over large dynamic power levels. For example, the bias network can have a frequency response, such as a high-pass or band-pass response, that reduces the impact of power level on phase distortion (AM/PM).

An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

A power amplifier includes power amplification circuits in a plurality of stages including a first stage and a second stage, each power amplification circuit including a transistor. The power amplification circuit in the first stage includes a first impedance circuit between an emitter of the transistor and a reference potential. The first impedance circuit has an impedance that does not vary with frequency or an impedance that varies with frequency. The power amplification circuit in the second stage includes a second impedance circuit between an emitter of the transistor and a reference potential. The second impedance circuit has an impedance that does not vary with frequency or an impedance that varies with frequency.

A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.

Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain droop due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.