A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.

A power amplifier circuit includes a power amplifier that amplifies an input signal and outputs the amplified signal from an output terminal thereof, a first filter circuit that has a frequency characteristic that attenuates an Nth-order harmonic of the amplified signal, N that is an integer greater than or equal to 2, and a second filter circuit that has a frequency characteristic that attenuates the Nth-order harmonic of the amplified signal. The first filter circuit includes a first capacitor and a first inductor. The first capacitor and the first inductor are connected in series between the output terminal and ground. The second filter circuit includes a second capacitor and a second inductor. The second capacitor and the second inductor are connected in series between the output terminal and ground.

Apparatus and methods for multi-mode power amplifiers are provided herein. In certain configurations, a wireless device includes a multi-mode power amplifier including a plurality of amplification paths electrically connected in parallel with one another. The plurality of amplification paths includes a first amplification path including an input stage of a first stage type and an output stage of a second stage type, and a second amplification path including an output stage of the second stage type. The first stage type provides non-inverting gain and the second stage type provides inverting gain. The wireless device further includes a transceiver that provides a radio frequency signal to the multi-mode power amplifier, and that operates the multi-mode power amplifier in a selected power mode chosen from a plurality of power modes based on selectively activating one or more of the plurality of amplification paths.

A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.

A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

The disclosed technology includes device, systems, techniques, and methods for amplifying a complex modulated signal with a mixed-signal power amplifier. A mixed-signal power amplifier may include an input network for splitting an input signal to multiple signals with corresponding phase and amplitude offsets, a main power amplification path including at least an analog power amplifier for amplifying a first signal, one or more auxiliary power amplification paths including at least one digitally controlled analog power amplifier in each path for amplifying a second signal, and an output network for combining the two amplified signals. The main power amplification path and the auxiliary power amplification paths can operate together to achieve load modulation to enhance the overall power amplifier efficiency at power back-off mode and the overall power amplifier linearity. The disclosed technology further includes transmission systems incorporating the mixed-signal power amplifier.

A hybrid RF transceiver circuit comprises a first matching network, a second matching network, a first power amplifier, a second power amplifier, and a low noise amplifier. The second matching network is coupled to the first matching network and an antenna. An output port of the first power amplifier is coupled to the first matching network and the second matching network. The output port of the second power amplifier is coupled to the first matching network. The input port of the low noise amplifier is coupled to the second power amplifier and the first matching network. The output port of the low noise amplifier is coupled to a receiver circuit.

A radio-frequency signal amplifier circuit that is used in a front-end circuit configured to propagate a radio-frequency transmission signal and a radio-frequency reception signal, includes an amplifier transistor configured to amplify the radio-frequency transmission signal, a bias circuit configured to supply a bias to a signal input terminal of the amplifier transistor, a resistor having one end connected to the bias circuit and the other end connected to the signal input terminal, and an LC series resonance circuit that has one end connected to a node n1 between the resistor and the signal input terminal and the other end connected to a grounding terminal. A resonant frequency fr of the LC series resonance circuit is included in a difference frequency band between the radio-frequency transmission signal and the radio-frequency reception signal.

The present invention relates to a four-way Doherty amplifier. The invention further relates to a mobile telecommunications base station.

The invention proposes a new Doherty combiner topology that allows peak efficiencies to be reached at deeper back-off levels than conventional Doherty combiners.