A ultra-compact coupler designed to sample the actual output power of a power amplifier and which is VSWR insensitive, such that reflected power is essentially not coupled to a detector circuit and only forward power is detected and processed. In a first embodiment, a coupler is situated between the final amplifier stage of a power amplifier and an output impedance matching network, and is specially configured for operation in a low impedance environment in conjunction with a detector circuit, thereby substantially reducing the areal size of the coupler. In a second embodiment, a coupler is integrated within an output impedance matching network coupled to the final amplifier stage of a power amplifier so as to share an inductor between the coupler and the output impedance matching network, thereby further substantially reducing the areal size of the coupler.

A ultra-compact coupler designed to sample the actual output power of a power amplifier and which is VSWR insensitive, such that reflected power is essentially not coupled to a detector circuit and only forward power is detected and processed. In a first embodiment, a coupler is situated between the final amplifier stage of a power amplifier and an output impedance matching network, and is specially configured for operation in a low impedance environment in conjunction with a detector circuit, thereby substantially reducing the areal size of the coupler. In a second embodiment, a coupler is integrated within an output impedance matching network coupled to the final amplifier stage of a power amplifier so as to share an inductor between the coupler and the output impedance matching network, thereby further substantially reducing the areal size of the coupler.

A power amplifier circuit, including: an input node configured to receive a radio frequency (RF) signal; an output node configured to output an amplified RF signal; a main path switchably coupled between the input node and the output node, and including a first plurality of amplification stages to generate a first amplified RF signal; a bypass path switchably coupled between the input node and the output node, and including at least one second amplification stage to generate a second amplified RF signal; and a coupling switch configured to reuse at least a portion of the bypass path to drive the main path to generate a third amplified RF signal.

A power amplifier circuit includes first and second transistors and a first voltage output circuit. A radio frequency signal is input into a base of the first transistor. The first voltage output circuit outputs a first voltage in accordance with a power supply voltage. The first voltage is supplied to a base or a gate of the second transistor. An emitter or a source of the second transistor is connected to a collector of the first transistor. A first amplified signal generated by amplifying the radio frequency signal is output from a collector or a drain of the second transistor.

A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.

An envelope tracking frontend device and a switch thereof are provided. The envelope tracking frontend device includes a power amplifier coupled, a switch and an envelope tracking module including an envelope tracking bias supply coupled between the signal generator and the switch. The switch includes a transmit-receive port, a transmit port coupled to the power amplifier, a receive port, a first terminal and a second terminal in series connection, and a third transistor and a fourth transistor as shunt transistors. The envelope tracking bias supply is configured to provide an envelope forward bias signal to the gate of the second transistor and the gate of the fourth transistor, and provide an envelope reverse bias signal to the gate of the first transistor and the gate of the third transistor such that an amplified signal is modulated before being provided by the switch.

A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.

Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.

A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.