An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.

A quasi-differential amplifier with an input port and an output port. The amplifier has a phase shifter network with a first port connected to the input port, a second port, and a third port. A first amplifier has an input connected to the second port of the phase shifter network, and an output, and a second amplifier has an input connected to the third port of the phase shifter network, and an output. A balun circuit includes a first differential port connected to an output of the first amplifier, a second differential port connected to an output of the second amplifier, and a single-ended port. An output matching network is connected to the single-ended port of the balun circuit and to the output port.

An apparatus includes multiple field effect transistors and multiple wires. An input wire may be configured to transfer an input signal along an axis. The field effect transistors may be configured to generate a pair of intermediate signals by amplifying the input signal. Multiple gates of the field effect transistors may be configured to receive the input signal. A topology of the gates may be rotated to be perpendicular to the axis. The field effect transistors may be located in two rows mirrored about the axis. Intermediate wires may be configured to transfer the intermediate signals parallel to the axis. A collection wire may be configured to transfer the intermediate signals toward each other and generate an output signal by combining the intermediate signals. An output wire may be configured to transfer the output signal parallel to the axis and away from the field effect transistors.

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path comprising a first amplification transistor and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path comprising a second amplification transistor and coupled between the input node and the output node, wherein the second amplification path further includes an attenuator coupled between the input node of the amplification circuit and a control input of the second amplification transistor.

Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.

A power amplifier circuit includes: a high pass filter that has one end into which a high frequency input signal is inputted; a first amplifier that amplifies the high frequency input signal outputted from the other end of the high pass filter and outputs a high frequency signal obtained through the first amplification; a second amplifier that amplifies the high frequency signal and outputs a high frequency output signal obtained through the second amplification; an automatic transformer that performs impedance matching between the first amplifier and the second amplifier; and an impedance circuit, one end of which is electrically connected with the other end of the high pass filter, the other end of which is electrically connected with an output terminal of a bias circuit outputting bias voltage or bias current to the first amplifier, and that outputs the high frequency input signal to the bias circuit.

Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain droop due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a first RF signal input terminal, a first RF signal output terminal, and a transistor. The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

A high frequency circuit includes a signal input terminal and a signal output terminal; a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier; and a first phase shift circuit. An input terminal of the fourth amplifier is connected to the signal input terminal, an output terminal of the fourth amplifier is connected to an input terminal of the first amplifier and an input terminal of the second amplifier, an output terminal of the second amplifier is connected to an input terminal of the third amplifier, an output terminal of the third amplifier is connected to one end of the first phase shift circuit, and the other end of the first phase shift circuit is connected to an output terminal of the first amplifier.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.