Apparatus and methods for multi-mode power amplifiers are provided herein. In certain configurations, a wireless device includes a multi-mode power amplifier including a plurality of amplification paths electrically connected in parallel with one another. The plurality of amplification paths includes a first amplification path including an input stage of a first stage type and an output stage of a second stage type, and a second amplification path including an output stage of the second stage type. The first stage type provides non-inverting gain and the second stage type provides inverting gain. The wireless device further includes a transceiver that provides a radio frequency signal to the multi-mode power amplifier, and that operates the multi-mode power amplifier in a selected power mode chosen from a plurality of power modes based on selectively activating one or more of the plurality of amplification paths.

A low noise amplifier includes a T-type circuit, a first amplification module and a second amplification module. The T-type circuit is adapted to receive an input signal from a signal source, filters the input signal to generate a filtered signal, and is configured such that an equivalent input impedance seen into the T-type circuit matches an equivalent output impedance seen into the signal source. The first amplification module is coupled to the T-type circuit for receiving the filtered signal therefrom, and amplifies the filtered signal to generate an amplified signal. The second amplification module is coupled to the first amplification module for receiving the amplified signal therefrom, and amplifies the amplified signal to generate an output signal.

A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.

A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

An amplifier with stacked transconducting cells in current mode combining is disclosed herein. In one or more embodiments, a method for operation of a high-voltage signal amplifier comprises inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I.sub.RF_IN), and an RF input signal (RF.sub.IN). The method further comprises outputting, by each of the transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (I.sub.RF_OUT). In one or more embodiments, the transconducting cells are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.

This application discloses a radio frequency switch circuit and an apparatus. An output end of a power amplifier (PA) output matching network is connected to an antenna, and an input end of the PA output matching network is connected to a PA. A low noise amplifier (LNA) input matching network includes a first coupling device, a second coupling device, and a switching device. The first coupling device is connected to the antenna, the switching device and the LNA, the switching device is connected to the second coupling device, and the second coupling device is connected to an LNA. This increases an output power of the PA output matching network and improves work efficiency.

Disclosed are a power amplifier and a method for controlling a power amplifier. The method includes providing an input signal to the first amplification path and the second amplification path; and supplying a first DC bias voltage and a second DC bias voltage to a control port of the third transistor and a control port of the fourth transistor respectively, where current conduction trenches of the third transistor and the fourth transistor comprise same materials and the first DC bias voltage is higher than the second DC bias voltage.

An apparatus is disclosed for implementing a clamping circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled thereto. The clamping circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.