Patent classifications
H03F2200/321
POWER AMPLIFIER AND RADIO FREQUENCY DEVICE COMPRISING THE SAME
A power amplifier is disclosed for amplifying an input signal and providing an amplified signal to a load at a junction node. The power amplifier comprises a splitter network, a carrier amplifier path and a peaking amplifier path. The peaking amplifier path comprises a first impedance transformer coupled between a peaking output matching network and the junction node to enhance the off-state impedance of the peaking amplifier. The carrier amplifier path comprises a second impedance transformer coupled between a carrier output matching network and the junction node.
Low complexity MIMO digital pre-distortion
A method and a transmitter arrangement for cancelling cross talk and correcting power amplifier (PA) distortion for a transmitter branch of a multiple-input multiple-output (MIMO) configuration having multiple branches. The method comprises combining an original baseband input signal of a first MIMO transmitter branch with a crosstalk output signal generated from two or more signals associated with two or more respective MIMO branches, the two or more signals used as input to, and processed by, a crosstalk model. The method further comprises processing the combined signal to generate an output signal in order to minimize the error of the original baseband input signal caused by the crosstalk and/or PA distortion.
ADJUSTING METHOD AND ADJUSTING SYSTEM FOR POWER AMPLIFIER
An object is to provide a method and a system of adjusting a power amplifier which makes it possible to adjust a linearizer using signals of two carriers by the same power, to reduce the influence of the non-linearity on a multicarrier signal compared with the conventional. A method of adjusting a power amplifier, the power amplifier including a linearizer to reduce an intermodulation caused by non-linearity of the power amplifier, includes: inputting two signals generated by a signal generator into the power amplifier; measuring power of each order of first intermodulations of the two signals output from the power amplifier; calculating a power sum of second intermodulations by the plurality of signals using the measured power of each order of the first intermodulations; and adjusting the linearizer so that the power sum of the second intermodulations by the plurality of signals takes a minimum value or at most a predetermined value.
Efficient operation of multi-carrier power amplifiers in dynamic carrier systems
System and method for efficient operation of power amplifiers in dynamic carrier systems. In one example, the method includes determining a composite RMS power and peak power for a carrier configuration of an RF transmitter, determining a number of active banks of power amplifiers as a function of composite RMS power and peak power, and determining a number of active power amplifiers within a bank of power amplifiers as a function of composite RMS power and peak power. The method also includes activating a first bank of power amplifiers and/or a second bank of power amplifiers based on the determined number of active banks of power amplifiers and activating a subset of a one or more first power amplifiers of the first bank of power amplifiers and a one or more second power amplifiers of the second bank of power amplifiers based on the determined number of active power amplifiers.
DC OFFSET CANCELLATION CIRCUIT AND DC OFFSET CANCELLATION METHOD
A DC offset cancellation circuit and a DC offset cancellation method are disclosed. The DC offset cancellation circuit comprises a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter. The high-speed amplifier comprises an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage. The voltage comparator is connected to the output buffer stage. The microprocessor is connected to the voltage comparator. The digital-to-analog converter is connected to the microprocessor. The digital-to-analog converter is connected to the input stage.
SYSTEM AND A METHOD FOR DETECTING LOUDSPEAKER CHAIN FAILURE
A method and a system for monitoring operation of at least one loudspeaker in a system comprising a plurality of loudspeakers connected in series on a same amplifier output in at least one loudspeaker chain driven by an amplifier board, the method comprising measuring a current consumed by the amplifier in an operating position of the plurality of loudspeakers, yielding a reference current; stopping the masking system into an idle position; emitting the reference signal, measuring an idle current consumed by the amplifier; and comparing the idle current with the reference current. The system comprises a microprocessor unit and a current measurement module, wherein the current measurement module is configured to measure a current drawn by the amplifiers and feed a resulting signal to the microprocessor unit; and the microprocessor unit generates an output signal to respective output channel.
Amplifier interface and amplification methods for ultrasound devices
Amplifier architecture that allows low-cost class-D audio amplifiers to be compatible with ultrasonic signals, as well as loads presented by thin-film ultrasonic transducers. The amplifier architecture replaces the traditional capacitor used as an output filter in the class-D amplifier with the natural capacitance of the ultrasonic transducer load, and employs relative impedance magnitudes to create an under-damped low-pass filter that boosts voltage in the ultrasonic frequency band of interest. The amplifier architecture includes a secondary feedback loop to ensure that correct output voltage levels are provided.
LOW NOISE AMPLIFIER CIRCUIT
An LNA circuit includes: paths provided between an input and an output terminals, an LNA provided in at least one path, and a selector selecting one path. The LNA includes: a MOS transistor coupled between a first and a second power supplies, a first inductor coupled to a source of the MOS transistor, a capacitor formed between a gate and the source of the MOS transistor, a second inductor coupled between the gate of the MOS transistor and the input terminal, and a changeover switch coupled parallelly with at least one of the capacitor, and the first and the second inductors. The selector switches between a first state that one path is selected and the changeover switch is on, and a second state that another path is selected and the changeover switch is off. Alternatively, the one path and the another path are respectively provided without and with the LNA.
Feed-forward envelope tracking
An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.
Feed-forward power amplifier with offline tuning capability
A method and base station transmitter for providing offline tuning of a base station transmitter. The base station transmitter includes a feed-forward power amplifier comprising a Radio Frequency (RF) input and an RF output. The base station transmitter also includes a simulated carrier generator operatively coupled to the feed-forward power amplifier prior to the carrier cancellation loop. The simulated carrier generator provides a simulated carrier signal including one or more individual carrier frequencies to the RF input. The base station transmitter also includes a processor that is operatively coupled to the feed-forward power amplifier and the simulated carrier generator. The processor performs tuning of a carrier cancellation loop using the simulated carrier signal when the processor determines that a carrier signal is not present.