An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

An uplink multiple input-multiple output (MIMO) transmitter apparatus includes a transmitter chain that includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from two original signals to be transmitted. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals match the two original signals in content but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. By employing this uplink MIMO transmitter apparatus, it is possible to use smaller power amplifiers, which may reduce footprint, power consumption, and costs of the uplink MIMO transmitter apparatus.

A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.

A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.

A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

An uplink multiple input-multiple output (MIMO) transmitter apparatus using transmit diversity uses transmit diversity signals that are modified to create intermediate orthogonal signals. A transceiver circuit in the transmitter apparatus includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from the intermediate orthogonal signals. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals correspond to the two original transmit diversity signals but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals.

An uplink multiple input-multiple output (MIMO) transmitter apparatus includes a transmitter chain that includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from two original signals to be transmitted. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals match the two original signals in content but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. By employing this uplink MIMO transmitter apparatus, it is possible to use smaller power amplifiers, which may reduce footprint, power consumption, and costs of the uplink MIMO transmitter apparatus.

An all-digital transmitter (ADT) is provided. The ADS includes a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band, a polyphase finite impulse response filter configured to receive and convert the baseband input signal into different phases, a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain, a set of multi-core 2-dimensional network-resonant digital plane wave beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle, a multi-core delta-sigma modulator configured to encode the upconverted input signal into pulsating signals, and a serializer configured to serialize the encoded pulsating signals into a RF bitstream.