A semiconductor device includes a carrier transit layer including a first region and second and third regions having a density of a donor impurity element higher than that of the first region, an In.sub.XAl.sub.YGa.sub.(1-X-Y)N (0<X<1, 0<Y<1, 0<X+Y1) carrier supply layer provided over the carrier transit layer and having a density of a donor impurity element lower than that of the second and third regions, a source electrode provided over the second region, a drain electrode provided over the third region, and a gate electrode provided over the carrier supply layer between the source electrode and the drain electrode.

The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.

The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S.sub.IN, and a first clock signal f.sub.SW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.

An amplifier circuits inductive/magnetic sensor interface can include a main signal path including one or more amplifiers configured to receive an input signal and to produce an output signal based on the input signal. The input signal may include a square-wave demodulated signal having an associated modulation frequency and an undesired frequency component at twice the modulation frequency of the square-wave demodulated signal. The amplifier circuit may include a gain feedback loop configured to set a gain of the amplifier circuit. The amplifier circuit may include a ripple reduction feedback loop configured to receive an intermediate signal on the main signal path and extract the undesired frequency component of the intermediate signal to produce a filtered version of the intermediate signal and provide the filtered version of the intermediate signal to the main signal path.

A radio frequency receiver having a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands.

An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (M.sub.CG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (M.sub.CG1) further having a first source (112) coupled to the first input (102). A second transistor (M.sub.CS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (M.sub.CS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (M.sub.CS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (M.sub.CS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (M.sub.CG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (M.sub.CG2) further having a fourth source (132) coupled to the second input (104). A first load (Z.sub.L1) is coupled between the first output (106) and a second voltage rail (136). A second load (Z.sub.L2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L.sub.1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L.sub.2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (M.sub.CG1) is substantially equal to transconductance of the fourth transistor

Disclosed are an apparatus and method of processing an audio signal to optimize audio for a room environment. One example method of operation may include recording the audio signal generated within a particular room environment and processing the audio signal to create an original frequency response based on the audio signal. The method may also include identifying a target sub-region of the frequency response which has a predetermined area percentage of a total area under a curve generated by the frequency response, determining whether the target sub-region is a narrow energy region, creating a filter to adjust the frequency response, and applying the filter to the audio signal.

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S.sub.IN, and a first clock signal f.sub.SW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability while reducing switching power losses.