A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

An RF frontend IC device includes an RF transceiver to transmit and receive RF signals and a frequency synthesizer to perform frequency synthetization to operate within a predetermined frequency band. The frequency synthesizer generates an LO signal to the RF transceiver to enable the RF transceiver to transmit and receive RF signals within the predetermined frequency band. The frequency synthesizer includes a QPG circuit to generate signals shifted in phases based on the LO signal and a phase shifting circuit to generate quadrant signals based on the signals shifted in phases. Each of the quadrant signals corresponds to one of the four quadrants in phases in the respective quadrant spaces. The phase shifting circuit includes multiple phase switches operable in a collaboration manner to further shift in phase based on the signal shifted in phases to generate the quadrant signals in proper quadrant spaces.

Circuit for wireless communication are provided, the circuits comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; a first mixer having a first input coupled to the first cpl port and having an output; a second mixer have a first input coupled to the first cpl port and having an output; a third mixer having a first input coupled to the first thru port and having an output; a fourth mixer having a first input coupled to the first thru port and having an output; and a first complex combiner having inputs coupled to the output of the first mixer, the output of the second mixer, the output of the third mixer, and the output of the fourth mixer that provides first I and Q outputs based the output of the first mixer and the output of the second mixer.

A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.

Described herein are systems and methods that manage polarization in coherent optical receivers by using analog signal processing that eliminates the need for ultra-fast, power-hungry ADCs and DSPs and that would require digitization of the full-bandwidth signal path and result in bulky and expensive circuit designs. Various embodiments of the invention provide polarization correction by using an analog polarization correction circuit that implements the equivalent of two matrix operations. This is accomplished by using analog electronics that comprises a combination of variable and unity gain amplifiers to align polarizations of input signals to generate a polarization-corrected output signal that is further aligned with the polarization frame of reference of the receiver.

It is configured to output a first I signal having passed through a first inverse characteristic circuit having inverse frequency characteristics to frequency characteristics of a first loop filter circuit, to the first loop filter circuit, and output a first Q signal having passed through a second inverse characteristic circuit having inverse frequency characteristics to frequency characteristics of a second loop filter circuit, to the second loop filter circuit.

Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage chained feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).

There is provided a technique for calibrating the envelope tracking circuitry of the wireless interface of an electronic device to compensate for any delay mismatch between the IQ signal path and the envelope path. The desired levels of input test signals are determined to assure that they are sensitive to any delay mismatch which may be in the system. The propagation delay from the signal generator to the signal analyzer of the envelope tracking system is estimated and delay compensation is performed. To reduce the noise of the measurement, distortion in the received signal may also be determined and noise compensation may also be performed. Based on these determinations, the envelope tracking circuitry may be calibrated by introducing an appropriate delay in either the envelope path or the IQ signal path.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.