Nonlinear bandwidth compression circuitry is provided. In examples discussed herein, nonlinear bandwidth compression circuitry can be configured to modify predefined amplitude(s) of a predefined voltage waveform to generate modified amplitude(s) of a modified voltage waveform that is never less than the predefined amplitude(s) of the predefined voltage waveform. Thus, by providing the nonlinear bandwidth compression circuitry in an envelope tracking (ET) system to perform bandwidth compression, signal distortion(s) resulted from the bandwidth compression can be corrected (e.g., via digital pre-distortion). As such, the ET system can amplify a radio frequency (RF) signal having a signal modulation bandwidth exceeding a voltage modulation bandwidth limitation of the ET system, without degrading spectral performance of the RF signal.

An apparatus is disclosed for amplification in presence of a variable antenna impedance. In an example aspect, the apparatus comprises a balanced power amplifier, which includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.

Methods and apparatuses for facilitating wide bandwidth power amplification with high efficiency for analog RF signals. A passive load modulated balanced amplifier (LMBA) device comprises a balanced power amplifier (BPA) and a directional coupler. The BPA comprises a first power amplifier (PA) configured to amplify a first portion of an input power, a second PA configured to amplify a second portion of the input power, an isolation port, and an output port that outputs the amplified first and second portions of the input power as an output power. The directional coupler is configured to provide a portion of the output power from the output port to the isolation port to modulate a load impedance of the first and second PAs.

A power amplifier control method is disclosed. A phase modulation control signal may be generated according to an envelope signal that is output by a baseband unit. The phase modulation may be performed on a signal of a main power amplifier link and/or an auxiliary power amplifier link in the Doherty power amplifier circuit according to the phase modulation control signal, so that a phase difference between the signal of the main power amplifier link and the signal of the auxiliary power amplifier link after the phase modulation is a specified value corresponding to a current value of the envelope signal, where the specified value is an optimal phase value of a Doherty power amplifier circuit when the supply voltage of the Doherty power amplifier circuit is an envelope voltage corresponding to the current value of the envelope signal. High-efficiency power amplifier technology is realized.

A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

An electronic apparatus according to one embodiment, includes: a signal generator generating a first signal and a second signal; a first characteristic circuitry acquiring first and second distorted signals by giving first and second distortion characteristic to the first and second signals; a first time-characteristic circuitry acquiring a third distorted signal by giving a first time-characteristic to the first distorted signal and acquiring a fourth distorted signal by giving a second time-characteristic to the second distorted signal; a second characteristic circuitry acquiring a fifth distorted signal by giving a second distortion characteristic to the third distorted signal, and acquiring a sixth distorted signal by giving the second distortion characteristic to the fourth distorted signal; and a processing circuitry estimating at least one of the first distortion characteristic and the second distortion characteristic based on the first signal, the second signal, the fifth distorted signal, and the sixth distorted signal.

A Doherty amplifier includes: a carrier amplifier that amplifies a first signal; a peak amplifier that amplifies a second signal; and a synthesis circuit that synthesizes the first signal amplified by the carrier amplifier and the second signal amplified by the peak amplifier, and the synthesis circuit includes a bandpass filter circuit that includes parasitic capacitances at respective output sides of the carrier amplifier and the peak amplifier as capacitors.

Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/? and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

A transmit in-phase quadrature (IQ) amplifier includes a common gain stage to receive an input signal and to generate an amplified signal. The amplifier includes an IQ poly-phase filter coupled to the common gain stage to receive the amplified signal from the common gain stage and outputs a four-phase signal. The amplifier includes an in-phase (I) phase switching gain stage coupled to the IQ poly-phase filter to receive I components of the four-phase signal and outputs an amplified phase switching I signal. The amplifier includes a quadrature (Q) phase switching gain stage coupled to the IQ poly-phase filter to receive Q components of the four-phase signal and outputs an amplified phase switching Q signal.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.