This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal () from the output signal and the input signal. In various embodiments the extent to which the error signal () contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

A distributed power management circuit is provided. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.

The present disclosure relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier. The modulator includes a pulse shaper and a control unit for controlling the pulse shaper to convert an input signal into a bit stream configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper can represent a respective amplitude value of the input signal with different bit patterns. The control unit includes an assignment of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier is stored or at least is provided in that the control unit selects a control command per clock by means of the assignment and the amplitude value of the input signal and drives the pulse shaper accordingly.

This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal () from the output signal and the input signal. In various embodiments the extent to which the error signal () contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).

A power amplifying apparatus includes a power circuit configured to generate operating power, a random pulse generation circuit configured to be supplied with the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time using an input radio frequency (RF) signal, and a charge pump circuit configured to be supplied with the operating power and to randomly perform a switching operation according to the pulse width modulation signal to generate a negative voltage.

The present invention relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier.

The modulator (100) comprises a pulse shaper (110) and a control unit (120) for controlling the pulse shaper (110) to convert an input signal into a bit stream (130) configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper (110) can represent a respective amplitude value of the input signal with different bit patterns. The bit pattern respectively used by the pulse shaper is determined by the control unit (120) by means of a corresponding, associated control command. The modulator (100) is characterized in that in the control unit (120) an assignment (160) of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier (400) is stored or at least is provided in that the control unit (120) selects a control command per clock by means of the assignment (160) and the amplitude value of the input signal and drives the pulse shaper (110) accordingly.

A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

A power amplifier includes an array of transistors having outputs that are connected in parallel to one another and coupled to an output network. The power amplifier further includes digital circuitry, configured to receive a sequence of control words that specify respective amplitudes of a signal to be transmitted in respective time intervals, and to transmit the signal by performing, for each control word and respective time interval: partitioning the control word into a Least Significant Bit (LSB) portion and a Most Significant Bit (MSB) portion; selecting a time duration based on the LSB portion; selecting an amplitude based on the MSB portion; and activating the array of transistors during the time interval in accordance with the selected time duration and the selected amplitude.

A power amplifying apparatus includes a power circuit configured to generate operating power, a random pulse generation circuit configured to be supplied with the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time using an input radio frequency (RF) signal, and a charge pump circuit configured to be supplied with the operating power and to randomly perform a switching operation according to the pulse width modulation signal to generate a negative voltage.