This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

A class-D amplifier that amplifies an input signal comprises a control circuit configured to generate a control signal that varies in accordance with a level of the input signal, a first generating circuit configured to generate a first pulse, and a second generating circuit configured to generate a second pulse. A pulse width of the first pulse becomes narrower as the signal level of the input signal becomes smaller, and the pulse width of the first pulse becomes wider as an instantaneous magnitude of the input signal becomes larger. A pulse width of the second pulse becomes narrower as the signal level of the input signal becomes smaller, and the pulse width of the second pulse becomes wider as an instantaneous magnitude of the input signal becomes smaller.

A switching amplifier comprises a controller, configured to receive an input signal and a reference signal, and to generate a control signal according to the input signal and the reference signal; a pulse-width modulation (PWM) modulator, coupled to the controller, configured to generate a PWM signal according to the input signal and the control signal; a power management unit, coupled to the controller, configured to receive a power supply and the control signal, and to provide an adaptive supply voltage according to the power supply and the control signal; and a switching power stage, coupled to the power management unit and the PWM modulator, configured to generate an output signal according to the PWM signal and the adaptive supply voltage.

A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

An audio circuit is configured to allow an analog voltage to be input via its volume setting pin. A power supply pin receives a power supply voltage. A bias circuit generates a first reference voltage that corresponds to the analog voltage. A D/A converter converts a digital audio signal into an analog audio signal. AD/A converter has a variable voltage range with a full scale that can be changed according to the first reference voltage. A class D amplifier outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal output from the D/A converter and having an amplitude that corresponds to the power supply voltage.

A system may include a forward signal path having a forward gain and configured to receive an input signal at an input and generate an output signal at an output as a function of the input signal, a feedback signal path having a feedback gain and coupled between the output and the input, and a control subsystem configured to operate the forward signal path and the feedback signal path in at least two modes comprising a first mode in which the forward gain is a first forward gain and the feedback gain is a first feedback gain and a second mode in which the forward gain is a second forward gain smaller than the first forward gain and the feedback gain is a second feedback gain larger than the first feedback gain. The control subsystem may cause operation in the first mode when signal content is present in the input signal and may cause operation in the second mode when signal content is absent from the input signal.

This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input to of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.

The present disclosure relates to a full-bridge class D amplifier comprising a first and second half-bridge circuit, wherein each half-bridge comprises a half-bridge output terminal between a high-side switch and a low-side switch. Wherein the first and second half-bridge circuits are controlled by a respective control signal to operate in differential mode with a predetermined switching frequency and wherein each half-bridge circuit further comprises an output terminal inductor connected between the half-bridge output terminal and ground. The amplifier further comprises a first and second coil coupled to form a common mode choke, wherein the first half-bridge output terminal is connected to an input terminal of the first coil, and wherein the second half-bridge output terminal is connected to an input terminal of the second coil .

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor. The system may additionally include a modulator for generating a differential pulse-width modulation driving signal to the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch and pilot tone injection circuitry configured to inject a periodic pilot tone into the differential pulse-width modulation driving signal at a pilot tone frequency.