Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Pulse width modulators 131P and 131N respectively generate a first pulse Vp whose pulse width changes according to an input signal Vin based on the input signal Vin and a generated first carrier wave C1P, and a second pulse Vn whose pulse width changes according to the input signal Vin based on the input signal Vin and a generated second carrier wave C1N. Wherein due to the non-liner gradient in each of the generated first carrier wave C1P and the generated second carrier wave C1N and, duty ratio of each of the generated first pulse Vp and the generated second pulse Vn is less than 50% in a state where a value of the input signal is zero; and a difference between a pulse width of the first pulse Vp and a pulse width of the second pulse Vn linearly changes according to the input signal Vin.

A class-D amplifier includes: a gain control unit that amplifies an input audio signal in accordance with a compensation gain to generate an input signal Vin; and a pulse width modulator that generates a first pulse Vp whose pulse width changes according to the input signal Vin within a first input range A1 where a value of the generated input signal Vin is higher than a first boundary Vb1, and that generates a second pulse Vn whose pulse width changes according to the generated input signal Vin within a second input range A2. The gain control unit controls the compensation gain so that first inclination of an input/output characteristic of the class-D amplifier in a first section in which the pulse width modulator outputs both the first pulse Vp and the second pulse Vn and second inclination of the input/output characteristic in a second section other than the first section are similar to each other.

A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.

An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.

A class-D amplifying system includes: a class-D amplifier circuit configured to convert an input signal to a switch control signal in pulse width modulation fashion, wherein the switch control signal controls switches to operate a first inductor and a second inductor, thus converting an input power to a positive output signal and a negative output signal which are complementary to each other, to thereby drive a load; and a power converter circuit, which generates a direct current (DC) power supply according to at least one of the positive output signal and the negative output signal, wherein the DC power supply supplies at least a portion of power to the class-D amplifier circuit.

A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.

A liquid ejecting apparatus includes an integrated circuit, and a feedback circuit that feeds back a feedback signal. The integrated circuit includes a modulation circuit that output a modulation signal, a constant voltage output circuit that outputs a DC voltage signal, and an input terminal to which the feedback signal is input. The modulation circuit and the constant voltage output circuit are electrically coupled to the input terminal, a first line segment located between the input terminal and the constant voltage output circuit in a first straight line connecting the input terminal and the constant voltage output circuit at a shortest distance does not intersect the modulation circuit, and a second line segment located between the input terminal and the modulation circuit in a second straight line connecting the input terminal and the modulation circuit at a shortest distance does not intersect the constant voltage output circuit.

A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.