Patent classifications
H03F2200/351
DC boost circuit and method
The present invention teaches a DC boost circuit and method. The circuit includes an inductor, a diode, a first capacitor, a first FET, a first voltage conversion unit, a voltage drop detection module, a reference voltage adjustment module, and a control module. After a load is connected, the voltage drop detection module obtains a current flowing through the diode and outputs a corresponding second voltage to the reference voltage adjustment module, causing an output voltage from the reference voltage adjustment module greater than an original reference voltage. The control module controls the first FET to increase a ratio of its conduction interval to its cutoff interval in a cycle of conduction and cutoff, thereby increasing the output voltage to compensate the voltage drop resulted from the impedance between the DC boost circuit and the load. The output voltage is therefore ensured to have a stable level.
Audio power source with improved efficiency
One example includes a differential amplifier, a voltage weighting element, coupled to a voltage source which provides an input voltage, to provide a reference voltage with a constant power limit when the input voltage varies, an error amplifier configured to receive and compare the reference voltage provided from the voltage weighting element and a feedback sensed voltage provided from the differential amplifier to identify whether the sensed voltage exceeds the reference voltage, and a pulse width modulation (PWM) controller, coupled to a power transformer and the error amplifier, that reduces a transformer input current provided to the power transformer based on the comparison of the reference voltage from the voltage weighting element and the feedback sensed voltage from the differential amplifier.
Minimizing crossover distortion in a class B current driver
A system may include an output stage comprising a single-ended driver for driving a load at an output of the output stage, a loop filter coupled at its input to the output of the output stage and configured to minimize an error between a target current signal received by the loop filter and an output current driven on the load, and control circuitry configured to, when the load current is driven in a manner such that the load current changes polarity, reset a state variable of the loop filter.
Class D power amplifier
A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.
SWITCHING POWER SUPPLY, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND DIFFERENTIAL INPUT CIRCUIT
This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.
COMMON MODE VOLTAGE CONTROLLER FOR SELF-BOOSTING PUSH PULL AMPLIFIER
Various implementations include systems for amplifying input signals. In particular implementations, a system includes a common mode voltage controller configured to receive an input signal and output a pair of adjusted signals; a modulator that generates a pair of pulse width modulation (PWM) signals in response to the adjusted signals; and a self-boosting push pull amplifier configured to receive the PWM signals and generate an amplified output, wherein the self-boosting push pull amplifier is configured to generate a differential mode voltage representative of an amplified version of the input signal, wherein the adjusted audio signals generated by the common mode voltage controller include a dynamically adjusted gain and duty cycle offset that causes the self-boosting push pull amplifier to operate with a reduced common mode voltage.
Audio power source with improved efficiency
Example embodiments provide a device that includes a power transformer with a first output voltage terminal providing a first voltage and a second output voltage terminal providing a second voltage, a voltage regulator coupled to one or more of the first output voltage terminal and the second output voltage terminal, and a power storage element that stores power supplied by the second output voltage, and the first output voltage terminal supplies power to a remote entity until a load power requirement of the remote entity exceeds a threshold power level at which time the power storage element is used to provide power from the second output voltage terminal to the remote entity.
Minimizing phase mismatch and offset sensitivity in a dual-path system
A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.
LOW POP-CLICK NOISE CLASS-D AMPLIFIER
A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.
LIQUID EJECTING APPARATUS AND DRIVE CIRCUIT
A liquid ejecting apparatus includes a drive circuit that outputs a drive signal, wherein the drive circuit includes a modulation circuit that modulates a base drive signal to output a modulation signal, an amplifier circuit that amplifies the modulation signal to output an amplified modulation signal, a demodulation circuit that demodulates the amplified modulation signal to output the drive signal, and a substrate on which the modulation circuit, the amplifier circuit, and the demodulation circuit are provided, wherein the substrate includes a first face and a second face opposite to the first face, wherein the demodulation circuit includes a first coil and a second coil electrically coupled in parallel with the first coil, and wherein the first coil is positioned so as to overlap at least part of the second coil in a direction normal to the first face.