Disclosed herein are implantable medical devices (IMDs) including a receiver and a battery, and methods for use therewith. The receiver includes first and second differential amplifiers, each of which monitors for a predetermined signal within a frequency range and drains power from the battery while enabled, and while not enabled drains substantially no power from the battery. To remove undesirable input offset voltages, each of the differential amplifiers, while enabled, is selectively put into an offset correction phase during which time the predetermined signal is not detectable by the differential amplifier. At any given time at least one of the first and second differential amplifiers is enabled without being in the offset correction phase so that at least one of the differential amplifiers is always monitoring for the predetermined signal. In this manner, the receiver is never blind to signals, including the predetermined signals, sent by another IMD.

The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

Various examples are directed to amplifier circuits and methods for operating amplifier circuits. The amplifier circuit may comprise a first amplifier stage. The first amplifier stage comprises a first amplifier, a first feedback resistance, a second amplifier, a second feedback resistance, and a gain resistance. A first current source may be electrically coupled to provide a first current across the gain resistance in a first direction. A second current source may be electrically coupled to provide a second current across the gain resistance in a second direction opposite to the first direction.

Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

A method for use in an analog circuit having a plurality of differential pairs of elements, wherein for each pair of the plurality of differential pairs of elements, the elements of the pair are designed to match but may have mismatch that induces error. The method includes, for each pair of at least two pairs of the plurality of differential pairs of elements: spectrally separating the mismatch-induced error of the pair from mismatch-induced error of a remainder of the plurality of differential pairs of elements, monitoring, by an analog-to-digital converter (ADC), an output of the analog circuit, and analyzing the monitored output to measure the mismatch-induced error of the pair.

A method for matching a pair of composite circuit elements (CEs) included in a circuit includes fabricating N CEs (e.g., resistors, transistors, current sources, capacitors) designed to match and switches configurable, according to M different combinations, to connect N/2 of the N CEs to form a first composite CE and to connect a remaining N/2 of the N CEs to form a second composite CE. Sequentially in time, for each combination of the M combinations, the switches are configured to form the first and second composite CEs according to the combination and a characteristic of the circuit is measured that includes the formed first and second composite CEs. The characteristic indicates how well the formed composite CEs match. A final combination of the M combinations is chosen whose measured characteristic indicates a best match and the final combination is used to configure the switches to form the composite CEs.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.

An operational amplifier includes an input stage with a first main input unit, a first auxiliary input unit, a second main input unit and a second auxiliary input unit, an amplification stage with a first current mirror receiving currents from the first main input unit and the first auxiliary input unit, and a second current mirror receiving currents from the second main input unit and the second auxiliary input unit, an output stage receiving voltages from the first current mirror and the second current mirror, a voltage storage unit storing an intermediate voltage based on an output signal generated by the output stage during at least one of a first operation period and a second operation period, and a switching unit that differently controls a first feedback path between the output stage and the input stage and a second feedback path between the output stage to the voltage storage unit in accordance with the first operation period and the second operation period.