An amplifier circuit for amplifying an input signal includes a transistor configured to receive the input voltage via an input port, and a second-harmonic trap connected between the transistor and ground, the second-harmonic trap having an impedance high enough to enable the second-harmonic trap to act as an open circuit at a second harmonic frequency of a voltage provided by the transistor. The second-harmonic trap includes a transformer including a primary winding connected to ground and a secondary winding, the primary winding receiving the voltage provided by the transistor. The second-harmonic trap further includes a variable capacitor connected in parallel with the secondary winding of the transformer, the variable capacitor having an adjustable capacitance that may be adjusted for the second-harmonic trap to act as the open circuit at the second harmonic frequency.

Provided is a low-noise amplifier that can effectively suppress noise included in an input signal. A low-noise amplifier according to an embodiment of the present invention amplifies a reception signal in a predetermined frequency band from an antenna. The low-noise amplifier includes an input terminal, an output terminal, a field effect transistor, and a branch circuit. The branch circuit is branched from a circuit connecting the input terminal or the output terminal to the field effect transistor. The branch circuit is connected to the elastic wave resonator.

A radio frequency (RF) front-end (RFFE) may include a differential hard-switching RF power amplifier. The RFFE may also include a ground bounce circuit coupled to the differential hard-switching RF power amplifier.

A power amplifier (PA) system is provided for multi-mode multi-band operations. The PA system includes one or more amplifying modules, each amplifying module including one or more banks, each bank comprising one or more transistors; and a plurality of matching modules, each matching module being configured to be adjusted to provide impedances corresponding to frequency bands and conditions. A controller dynamically controls an input terminal of each bank and adjusts the matching modules to provide a signal path to meet specifications on properties associated with signals during each time interval.

A transmitter for transmitting a signal is provided, in which the transmitter includes a power amplifier and a driver amplifier, an output of the driver amplifier being connected to an input of the power amplifier via a first load modulation device operable to match impedance of the driver amplifier output with impedance of the power amplifier input. A second load modulation device can be connected to the output of the power amplifier and operable to match the impedance of the power amplifier output with input impedance of a further device. Envelope tracking can be applied to the power amplifier and the driving amplifier.

A polar transmitter includes an amplitude path comprising an amplitude signal that corresponds to an amplitude of a vector sum of an in-phase input signal and a quadrature input signal; a phase path comprising a phase modulator configured to phase-modulate a phase signal that corresponds to the phase of the vector sum of the in-phase input signal and the quadrature input signal; a digital power amplifier (DPA) configured to amplify the phase-modulated (PM) input signal based on the amplitude signal; a tunable matching network coupled to an output of the DPA and configured to adjust a load impedance of the DPA; and a controller configured to adjust the matching network based on a look-up table with respect to amplitude and frequency information, where the look-up table indicates a plurality of optimal operation modes of the matching network for specific combinations of amplitude and frequency information.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

A tunable amplifier includes continuous tunability for both frequency and power levels. The tunable amplifier includes a combination of a tunable series resonator and a multi-stage LC network as the output matching network. The tunable amplifier incorporates a variable diode varactor with high breakdown voltage and high tuning range into a tunable resonator. The tunable resonator is connected to a fixed output matching network to enable a wide range of operating frequencies. The tunable amplifier enables high power, high efficiency, broadband and load-modulated power amplification, which is greatly desired for next-generation wireless communication systems and other high-frequency applications.

Aspects of this disclosure relate to systems and methods of performing dynamic impedance tuning. Certain aspects may be performed by or include a dynamic impedance matching network. The dynamic impedance matching network can determine a desired output power for a power amplifier, true power information for the power amplifier, and an output power delivered to a load by the power amplifier. In addition, the dynamic impedance matching network can determine whether the output power satisfies the true power information. Responsive to this determination, the dynamic impedance matching network may modify a load line impedance for the power amplifier using an impedance tuning network.

In an RFIC provided in a semiconductor device according to an embodiment, a low-noise amplifier (41) for reception and a power amplifier (11) for transmission are connected to a common antenna connection terminal (5). Between the antenna connection terminal (5) and an LNA (41), a circuit (31) is connected to be used for impedance matching, and a semiconductor switch (SW1) is connected in parallel with the circuit (31).