Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.

A variable gain amplifier according to an embodiment comprises a first path, a matching circuit, an amplifier circuit, a second path, and a third path. The first path includes an attenuation circuit, has one end connected to a first input terminal, and attenuates an input signal and outputs an attenuated signal. The matching circuit has one end connected to the other end of the first path. The amplifier circuit has an input connected to the other end of the matching circuit and an output connected to a first output terminal, and amplifies an input signal. The second path is connected in parallel to the first path. The third path has one end connected to the first input terminal, and the other end connected to the first output terminal.

A signal processor and method. The signal processor includes a signal current path. The signal processor includes a transconductor. The transconductor has an input operable to receive an input voltage of the signal processor. The transconductor also has an output operable to output a current based on the input voltage. The signal processor also includes a processing stage coupled to the output of the transconductor to receive and process the current outputted by the transconductor. The signal processor further includes a current replicator operable to generate a replica current proportional to the current outputted by the transconductor. The signal processor also includes a comparator operable to compare an output of the current replicator with a reference. The signal processor further includes a current limiter operable to limit the current outputted by the transconductor based on the comparison of the output of the current replicator with the reference.

An audio processing circuit includes a cascade operational amplifier circuit, an output node, and a pull-down circuit. The cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit includes a main operational amplifier and a secondary operational amplifier that are connected in parallel. The pull-down circuit is configured to pull down a voltage at the output node after the first operational amplifier circuit is turned on. The second operational amplifier circuit is configured to, after the secondary operational amplifier is turned on, control a voltage gain of the secondary operational amplifier to change gradually from low to high.

In a signal path comprising an analog path portion configured to operate in a plurality of output impedance modes including a high impedance mode with a first impedance and a low impedance mode with a second impedance, and a digital path portion having a variable digital gain and configured to convert a digital input signal and into an analog signal provided to the analog path portion, a method may include responsive to a condition for switching between the high impedance mode and the low impedance mode or vice versa, transitioning the output impedance continuously or in a series of steps between the first impedance and the second impedance or vice versa and, contemporaneously with transitioning the output impedance, transitioning the variable digital gain continuously or in a series of steps such to maintain a substantially constant overall path gain for the signal path remains substantially constant during transition.

An audio processing circuit includes a cascade operational amplifier circuit, an output node, and a pull-down circuit. The cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit includes a main operational amplifier and a secondary operational amplifier that are connected in parallel. The pull-down circuit is configured to pull down a voltage at the output node after the first operational amplifier circuit is turned on. The second operational amplifier circuit is configured to, after the secondary operational amplifier is turned on, control a voltage gain of the secondary operational amplifier to change gradually from low to high.

Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.