A linear low noise amplifier is disclosed. In at least one exemplary embodiment, the linear low noise amplifier may include a first metal oxide semiconductor field effect transistor (MOSFET) configured to operate in a triode mode coupled to a second MOSFET configured to operate in a saturation mode. Linearity of the low noise amplifier may be determined, at least in part, by a transconductance associated with the second MOSFET and a channel resistance associated the first MOSFET.

An apparatus includes a multi-stage amplifier and a feedback switch. The multi-stage amplifier includes a first amplifier having a first input, a second input, and an output, a second amplifier having an input and an output, wherein the input of the second amplifier is coupled to the output of the first amplifier, and a third amplifier having an input and an output, wherein the input of the third amplifier is coupled to the output of the first amplifier. The feedback switch is coupled between the output of the third amplifier and the second input of the first amplifier.

A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.

A linear low noise amplifier is disclosed. In at least one exemplary embodiment, the linear low noise amplifier may include a first metal oxide semiconductor field effect transistor (MOSFET) configured to operate in a triode mode coupled to a second MOSFET configured to operate in a saturation mode. Linearity of the low noise amplifier may be determined, at least in part, by a transconductance associated with the second MOSFET and a channel resistance associated the first MOSFET.

A differential signal is input to a pair of gates of a differential pair, a differential signal generated by a load circuit connected to drains of the differential pair is amplified by a differential amplifier stage, and the amplified differential signal is fed back to a pair of sources of the differential pair via a feedback circuit. It is possible to maintain a high input impedance in the pair of gates of the differential pair while not being influenced by a gain of negative feedback of an amplifier circuit, and it is possible to perform amplification in an input stage by using a pair of a first transistor and a second transistor of the differential pair. Therefore, compared with the related art, it is possible to decrease the number of transistors in the input stage and to reduce a flicker noise.

An amplifier circuit is provided. The amplifier circuit includes an amplifier stage; a plurality of variable transistors connected to the amplifier stage; a transconductor connected to at least one of the plurality of variable transistors; and a hybrid differential envelope detector and full-wave rectifier connected to the transconductor.

A dynamically biased baseband current amplifier is provided. The dynamically biased baseband current amplifier includes an input interface; a controller; a variable resistor network; an amplifier stage; a hybrid differential envelope detector and full-wave rectifier; a transconductor; a first variable transistor; a second variable transistor; a third variable transistor; and a fourth variable transistor.

Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

A tracker circuit is provided that includes a voltage generation circuit configured to generate multiple discrete voltages based on an input voltage; and a supply modulator configured to select a voltage from among the multiple discrete voltages, and to output the selected voltage in parallel to a first power amplifier and a second power amplifier. The first power amplifier is connected to an antenna and configured to amplify a millimeter-wave signal, and the second power amplifier is connected to an antenna different from the antenna and configured to amplify the millimeter-wave signal.

A radio frequency circuit is provided that includes a power amplifier connected to an antenna and configured to amplify a millimeter-wave signal; a power amplifier connected to an antenna different from the antenna and configured to amplify the millimeter-wave signal; a voltage generation circuit configured to generate multiple discrete voltages based on an input voltage; a first supply modulator configured to selectively output one of the multiple discrete voltages to the power amplifier; and a second supply modulator configured to selectively output one of the multiple discrete voltages to the power amplifier. The first and second supply modulators are configured to select a same voltage from among the multiple discrete voltages in accordance with a first digital control signal.