Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.

A RF amplifier is provided that includes a plurality of switch modules connected in a cascade configuration and divided into disjoint sets in accordance with their corresponding distinct peak DC voltages or currents, each switch module including a plurality of switch devices connected in a half-bridge or full-bridge circuit and a DC voltage or current source electrically connected with the half-bridge or full-bridge circuit, and a control circuit configured to determine an output voltage or current of the RF amplifier at the next switching interval, examine the states of the switching devices in the respective switch modules to identify a combination of least-recently-switched switching devices within each set of switch modules that, when switched to an opposite state, will produce the determined output voltage or current, and switch to an opposite state, at the next switching interval, the switching devices in the identified combination.

According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 μm to 1 mm, a width of the at least one line is ⅓ or less of a width of the first plane, and a pattern ratio is 1 or more.

A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.

There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.

A low-noise amplifier is provided. The low-noise amplifier includes a first transistor configured to amplify an input signal; a second transistor which forms a cascade structure with the first transistor and configured to amplify an output signal of the first transistor; and a third transistor which forms a cascode structure together with the first transistor and configured to amplify the output signal of the first transistor, wherein a first signal including a sum of the output signal of the second transistor and the output signal of the third transistor is output to an output terminal.

A power converter converts a digital input signal into an RF output power signal. A digital signal processor converts the input signal into one or more copies of a multi-bit RF signal. Each copy of the multi-bit RF signal is applied to a corresponding multi-bit current generator having a set of weighted, switched current sources, each of which is controlled by a different bit of the multi-bit RF signal. The currents from the different current sources are processed and combined to generate the output power signal.

An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source.

A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.

Embodiments of the disclosure are drawn to apparatuses a hybrid switched capacitor array power amplifier (H-SCPA). The H-SCPA may have an array of storage elements divided into sub-arrays. A first sub-array may be configured to receive a delta sigma modulated (DSM) signal. A second sub-array may be configured to receive a Nyquist-rate signal. The H-SCPA may provide an output based on the received DSM and Nyquist-rate signals. The first sub-array and second sub-array may have different architectures. The DSM signal may represent the least significant bits of the signal and the Nyquist-rate signal may represent the most significant bits of the signal.