The present disclosure relates to a full-bridge class D amplifier comprising a first and second half-bridge circuit, wherein each half-bridge comprises a half-bridge output terminal between a high-side switch and a low-side switch. Wherein the first and second half-bridge circuits are controlled by a respective control signal to operate in differential mode with a predetermined switching frequency and wherein each half-bridge circuit further comprises an output terminal inductor connected between the half-bridge output terminal and ground. The amplifier further comprises a first and second coil coupled to form a common mode choke, wherein the first half-bridge output terminal is connected to an input terminal of the first coil, and wherein the second half-bridge output terminal is connected to an input terminal of the second coil .

An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

A device is provided including a power transistor at an output node, which is coupled to a load terminal of the power transistor. A DC feed path is also provided. One or more discrete capacitors are coupled between the DC feed path and a reference potential. A first capacitor of the one or more discrete capacitors which is closest to the output node is a trench capacitor device.

A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node.

Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.

A power amplifier including: a main power amplification device having an output; an auxiliary power amplification device having an output; a load modulation circuit operably connected to the output of the main power amplification device and the output of the auxiliary power amplification device; and a post-matching circuit operably connected to load modulation circuit. The load modulation circuit is arranged to enable fundamental frequency load modulation and to enable modulated harmonic terminations of at least the second and third harmonic frequencies. The modulated harmonic terminations may include drain terminations.

An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground. The input-side and output-side harmonic termination circuits resonate at a harmonic frequency of a fundamental frequency of operation of the amplifier.

A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x≈1.5).

A semiconductor device includes a semiconductor chip mounted on an upper surface of a base substrate and having an output pad, a first capacitive component mounted on the upper surface of the base substrate and having one end electrically connected to the base substrate, a frame provided on the base substrate and made of a dielectric surrounding the semiconductor chip and the first capacitive component, an output terminal provided on the frame, a wiring pattern provided on an upper surface of the frame, a first bonding wire electrically connecting the output pad to the output terminal, a second bonding wire electrically connecting another end of the first capacitive component to a first region in the wiring pattern, and a third bonding wire electrically connecting the output pad to a second region different from the first region in the wiring pattern.

An amplifying system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The amplifying system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.