Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an RF I/O (e.g., an input or output lead). The video bandwidth circuit is coupled between a connection node of the impedance matching circuit and a ground reference node. The video bandwidth circuit includes a plurality of components, which includes an envelope inductor and an envelope capacitor coupled in series between the connection node and the ground reference node. The video bandwidth circuit further includes a first bypass capacitor coupled in parallel across one or more of the plurality of components of the video bandwidth circuit.

Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies.

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an RF I/O (e.g., an input or output lead). The video bandwidth circuit is coupled between a connection node of the impedance matching circuit and a ground reference node. The video bandwidth circuit includes a plurality of components, which includes an envelope inductor and an envelope capacitor coupled in series between the connection node and the ground reference node. The video bandwidth circuit further includes a first bypass capacitor coupled in parallel across one or more of the plurality of components of the video bandwidth circuit.

A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. The output circuit is coupled between the first current carrying terminal and an output lead. The output circuit includes first and second inductive elements coupled in series. The first inductive element, which may be a first bondwire array or an integrated inductance, is coupled between the first current carrying terminal and a node. The second inductive element, which includes a second bondwire array, is coupled between the node and the output lead. The device also includes a shunt circuit with a shunt capacitor and a third bondwire array coupled between the first current carrying terminal and the shunt capacitor. The first and second inductive elements and the third bondwire array are configured to have a desired mutual inductance.

A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node.

Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies.

A Doherty amplifier includes a divider configured to divide an input signal into two signals, a first amplifier configured to amplify one of the two signals and output the amplified signal to a first node, a second amplifier configured to amplify the other of the two signals and output the amplified signal to a second node, a balun including lumped parameter elements and configured to output a signal obtained by combining the signal output from the first amplifier with the signal output from the second amplifier to a third node, and a path configured to DC-connect the first node to the second node, with the third node therebetween.

A wideband amplifier includes an input matching network for matching a transconductor stage to an input impedance and includes an output matching network for matching the transconductor stage to an output impedance. Both the input and output matching networks each includes a parallel LC tank circuit arranged in parallel with a series LC tank circuit. The tank circuit arrangements configure the input and output matching networks to be resonant at a first frequency, a midrange frequency that is greater than the first frequency, and a second frequency that is greater than the midrange frequency to provide wideband matching.