An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.

A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.

Disclosed are a radio frequency power amplifier for inhibiting a harmonic wave and stray, a chip and a communication terminal. The radio frequency power amplifier comprises a power source, an LDO circuit, a harmonic inhibition unit, a stray inhibition unit, an amplifying unit, and a low-pass matching network. On the one hand, by means of the power source being connected to the harmonic inhibition unit, harmonic waves and stray of the power source at a resonant frequency are inhibited. Additionally, by means of the stray inhibition unit reducing the gain of the amplifying unit at a resonant frequency, output of stray is reduced. On the other hand, by means of the low-pass matching network being embedded at an output end of the radio frequency power amplifier, harmonic waves and the stray of a radio frequency signal amplified by the amplifying unit at different frequencies is effectively inhibited.

An amplification unit contains two or more sets containing a plurality of amplification circuits, and amplifies power of an RF (Radio Frequency) signal. A combining unit contains two or more combiners corresponding to the two or more sets, combines RF signals output by the amplification circuits, and outputs a resultant RF signal. The amplification unit and the combining unit have two or more connectors which are arranged transversely. The amplification unit and the combining unit are attachable/detachable.

A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

Within a modulator driver, different blocks are employed, e.g. a buffer, one or more variable gain amplifiers (VGA), and a final driver stage. Each of these blocks has an optimum bias point for best performance; however, interconnecting the blocks requires sharing the DC bias points in their interface, which does not necessarily match the optimum performance bias point of each block.. Accordingly, a first offset feedback loop extending from reference points after a selected one of the blocks to an input of one of the blocks. The first offset feedback loop includes current sources capable of delivering a variable current to the input of the selected block in order to compensate any offset in an amplified differential input electrical signal measured at the reference points. A first bias feedback loop is also provided, including a current sinker for subtracting excess current introduced in the first offset compensation feedback loop.

An amplifier, e.g., a low-noise amplifier, includes a field-effect transistor having a one-dimensional channel. This channel includes a semiconductor material for conducting electrons along a main direction of the channel. This direction is perpendicular to a cross-section of the channel. Dimensions of this cross-section are, together with the semiconductor material, such that the channel exhibits quantized conduction of electrons along its main direction. The amplifier further includes an electrical circuit that is configured to operate the transistor at a value of gate-to-source voltage bias corresponding to a peak value of a peak of a transconductance of the channel with respect to gate-to-source voltage bias values.

A sub-40 kilohertz low-frequency cutoff is provided for via a transimpedance amplifier comprising differential inputs and differential outputs; coupling capacitors comprising input terminals configured to receive electrical signals, and output terminals coupled to the differential inputs; and feedback paths coupled to the differential outputs and operable to level shift voltage levels at the input terminals. In some embodiments, the feedback paths comprise source follower transistors wherein the differential outputs are coupled to gate terminals of the source follower transistors or the feedback paths further comprise feedback resistors. In some embodiments, a bias resistor is coupled between the differential inputs.

A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.

A receiver signal path includes a high pass filter that centers a received differential pair of signals around a common mode voltage to generate a centered received differential pair of signals. The receiver signal path includes a demodulator that removes a carrier signal from the centered received differential pair of signals to generate a demodulated signal and generates a logic signal based on the demodulated signal and a predetermined threshold signal. The demodulator includes a differential stage including an extremum selector circuit that generates the demodulated signal based on the centered received differential pair of signals. The demodulated signal corresponds to a mean level of the rectified version of the centered received differential pair of signals. The differential stage includes a second circuit that provides the reference signal based on the predetermined threshold signal. The logic signal is based on a comparison of the demodulated signal to the reference signal.