The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure is to amplify transmission signals in a wireless communication system, and a transmitting device may include an antenna array including a plurality of antenna elements, a plurality of amplification chains for amplifying signals transmitted through the plurality of the antenna elements, and a power supply line for supplying powers to the plurality of the amplification chains. Herein, the powers used by power amplifiers included in at least one amplification chain of the plurality of the amplification chains may be divided by filtering or by independent pads and branch-lines.

A bias circuit includes a current mirror circuit, an operational amplifier, and a bias generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a base current, and the at least one mirror branch circuit generates at least one mirrored current according to the reference current. The operational amplifier receives a first voltage from the reference branch circuit and a second voltage from the at least one mirror branch circuit, and adjusts the first voltage by generating a control voltage according to the second voltage. The bias generating circuit is coupled to the at least one mirror branch circuit and generates a bias signal according to the at least one mirrored current.

A power amplifier circuit includes power amplifiers connected in stages to amplify a high-frequency input signal and to output an amplified high-frequency output signal, bias circuits each of which outputs a bias current to a corresponding one of the power amplifiers, and a bias control circuit configured to output a bias control current based on a second reference potential that varies in response to power of the high-frequency output signal and that is a potential of a portion in one bias circuit of the bias circuits to one or more bias circuits in a stage preceding the one bias circuit for increasing a bias current outputted from the one or more bias circuits in the stage preceding the one bias circuit.

An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

A differential power amplifier includes an input matching network, a first-stage amplification circuit, a first inter-stage matching network, a second-stage amplification circuit, a second inter-stage matching network, a third-stage amplification circuit, and an output matching network. The first-stage amplification circuit and the second-stage amplification circuit are single-ended input single-ended output circuits. The third-stage amplification circuit is a dual input dual output circuit. The second inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The output matching network includes a second transformer T2. The inter-stage matching networks and the output matching network are realized by the first transformer T1 and the second transformer T2, which reduces an inter-stage matching difficulty, optimizes input return loss and gain, and improves output power.

A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

Provided is a temperature detection circuit that includes: a series connection circuit that is connected between a power supply voltage input terminal and ground and includes a temperature detection transistor and a first resistance element; and a current bypass circuit that includes a first transistor that is connected in parallel with the temperature detection element and allows a bypass current to flow therethrough. The temperature detection circuit outputs a temperature detection signal from a connection point between the temperature detection transistor and the first resistance element.

A CMOS trans-impedance amplifier includes an inverting amplifier circuit and a feedback resistor. The inverting amplifier circuit includes an input end and an output end, and the feedback resistor is coupled therebetween. The inverting amplifier circuit includes at least three sequentially-connected amplifier units, and each amplifier unit includes at least three sequentially-connected nFETs, namely an input signal receiving part nFET, an intermediate part nFET and a DC signal receiving part nFET. A common connection terminal of the input signal receiving part nFET and the intermediate part nFET is configured to output an amplified voltage signal.

A programmable transimpedance amplifier (TIA) includes a plurality of signal paths between an output of a common emitter amplifier and the output of the TIA. The TIA is programmed by selecting one of the signal paths, because the paths have different parameters (e.g. different bandwidth). Thus, the bandwidth or other parameter can be programmed by selecting the appropriate path. The common emitter amplifier's output is coupled to the inputs of common base amplifiers in each path. The inputs have low impedance. Also, each path has a separate buffer amplifying the common base amplifier output in the path. Therefore, having multiple paths does not significantly degrade the amplifier performance. High bandwidth can be provided.