A consecutive Doherty amplifier is disclosed. The Doherty amplifier includes a carrier amplifier, a power splitter, a peak amplifier, and a phase compensator. The carrier amplifier receives a radio frequency signal with interposing any signal splitters. The power splitter splits an output of the carrier amplifier into first and second split signals. The phase compensator transfers the second split signal to the peak amplifier. The first split signal is combined with the output of the peak amplifier.

An operational amplifier includes a differential amplification circuit configured to receive and amplify an input voltage to generate an output voltage, and receive a feedback signal, and the feedback signal adjusts a common-mode voltage of the output voltage, a reference voltage generation circuit configured to detect status information of the operational amplifier, and generate a reference voltage based on the status information, where the status information includes a temperature or an operating voltage of the operational amplifier, and a common-mode feedback circuit configured to receive the output voltage and the reference voltage, and provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage.

In optical receivers, extending the transimpedance amplifier's (TIA) dynamic range is a key to increasing the receiver's dynamic range, and therefore increase the channel capacity. Ideally, the TIA requires controllable gain, whereby the receiver can modify the characteristics of the TIA and/or the VGA to process high power incoming signals with a defined maximum distortion, and low power incoming signals with a defined maximum noise. A solution to the problem is to provide TIA's with reconfigurable feedback resistors, which are adjustable based on the level of power, e.g. current, generated by the photodetector, and variable load resistors, which are adjustable based on the change in impedance caused by the change in the feedback resistor.

A multi-stage amplifier with a high signal-to-noise ratio is introduced. Multiple amplification stages are cascaded between an input terminal and an output terminal of the amplifier. A controller switches the output stage among the multiple amplification stages from a normal mode to an attenuation mode in response to the amplifier input being lower than the threshold. In the attenuation mode, the output stage provides an attenuation resistor coupled in series with the load resistor of the amplifier. Noise is successfully attenuated by the attenuation-mode output stage.

The present general inventive concept is directed to a method and system to generate a power signal, including summing a non-inverted reference signal and an inverted feedback signal to output a non-inverted first summation signal, summing an inverted reference signal and a non-inverted feedback signal to output an inverted second summation signal, receiving the first summation signal at a non-inverted input of a differential power output driver, and the second summation signal at an inverted input of the differential power output driver, outputting a non-inverted power signal to a first terminal of an impedance load from a non-inverted output of the differential power output driver, and outputting an inverted power signal to a second terminal of the load from an inverted output of the differential power output driver, the non-inverted power signal also being used as the non-inverted feedback signal, and the inverted power signal also being used as the inverted feedback signal.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.

A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.

An amplifying device includes a current generating circuit, a bias amplifying circuit, and a compensation circuit. The current generating circuit is configured to generate an internal current based on an internal voltage. The bias amplifying circuit, connected to the current generating circuit, is configured to output a bias current generated by amplifying the internal current to a power amplifying circuit. The compensation circuit, connected to the current generating circuit, is configured to adjust the internal voltage based on a bias voltage of the power amplifying circuit.