A solid-state amplifier architecture is disclosed. In some embodiments, the disclosed architecture may include first and second channel chipsets configured to amplify either the entire instantaneous frequency band of a radio frequency (RF) input signal or, respectively, sub-bands thereof, which may be divided proportionally between the two chipsets. In some cases, the chipsets may be configured to amplify frequencies in excess of the entire K-band and K.sub.a-band frequencies simultaneously. In some cases, the architecture may be configured to address a signal received, for instance, from an electronic warfare (EW) system to a log amplifier stage configured to output a signal to the EW system, in response to which the EW system may generate a RF signal for amplification by the architecture for transmission. To facilitate heat dissipation, the architecture may be coupled, in part or in whole, with a thermally conductive carrier, optionally with an intervening diamond heat spreader layer.

A power amplifier circuit includes a first amplifier that amplifies a first signal, and a second amplifier arranged subsequent to the first amplifier. The second amplifier amplifies a second signal that is based on an output signal of the first amplifier. The first amplifier performs class inverse-F operation, and the second amplifier performs class F operation.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A multi-voltage generation circuit and related envelope tracking (ET) amplifier apparatus is provided. In one aspect, a multi-voltage generation circuit is configured to generate a number of ET target voltages based on an analog voltage signal. In another aspect, a multi-amplifier ET circuit can be configured to include a number of amplifier circuits for amplifying concurrently a radio frequency (RF) signal based on a number of ET voltages. The multi-amplifier ET circuit also includes a number of driver circuits configured to generate the ET voltages base on a number of ET target voltages. In this regard, the multi-voltage generation circuit can be provided in the multi-amplifier ET circuit to generate the ET target voltages based on the analog voltage signal that corresponds to the RF signal. In examples discussed herein, the driver circuits are co-located with the amplifier circuits to help improve efficiency and maintain linearity in the amplifier circuits.

Gain is suppressed. In a power amplification circuit, a first transistor has a first input terminal, a first output terminal, and a first ground terminal. A second transistor has a second input terminal, a second output terminal, and a second ground terminal. The second input terminal is connected to the first input terminal. The second output terminal is connected to the first output terminal. A first bias circuit is connected to the first input terminal. A second bias circuit is connected to the second input terminal. A first resistor is connected between the first ground terminal and the ground. A second resistor is connected between the second ground terminal and the ground. The second resistor has a resistance value greater than that of the first resistor.

In one implementation, a circuit can include a reference pin and an operational amplifier that can include an output pin, an inverting input pin and a non-inverting input pin. The inverting input pin can be electrically coupled to the output pin via a first impedance and to the reference pin via a second impedance. The non-inverting input pin can be electrically coupled to the reference pin via a third impedance and can be configured to receive a detection signal. The reference pin can be configured to receive a detection reference signal associated with the detection signal.

A power amplifier apparatus includes: an amplifier configured to amplify an input signal; a sensing circuit connected to the amplifier and configured to sense a bias of the amplifier; and a biasing circuit connected to the sensing circuit and configured to provide a biasing current to the amplifier, wherein the sensing circuit is configured to change the biasing current based on the bias of the amplifier.

An amplifier transistor operates in two operation modes having different characteristics. A first bias circuit including a first bias supply transistor supplies an output current of the first bias supply transistor to the amplifier transistor as a bias current. A second bias circuit including a second bias supply transistor supplies a portion of an output current of the second bias supply transistor to the amplifier transistor as a bias current. At least one of the first bias circuit and the second bias circuit is selected and operates in accordance with an operation mode of the amplifier transistor by using a bias control signal input to a bias control terminal. The second bias circuit includes a current path along which a portion of the output current of the second bias supply transistor is returned to the second bias circuit.

In one embodiment, an electronic system includes a printed circuit board, one or more packaged semiconductor devices, and a vapor chamber having a top and a bottom and enclosing a sealed cavity that is partially filled with a coolant. The vapor chamber comprises a thermo-conductive and electro-conductive material. The top of the vapor chamber has one or more depressions formed therein, each depression receiving and thermo-conductively connected to at least part of a bottom of a corresponding packaged semiconductor device, which is mounted through a corresponding aperture in the PCB. A heat sink may be thermo-conductively attached to the bottom of the vapor chamber.

Radio Frequency (RF) amplifiers with voltage limiting using non-linear feedback are presented herein. According to one aspect, an RF amplifier comprises an amplifier circuit having an input terminal and an output terminal and a non-linear feedback circuit having an input terminal and an output terminal. The input terminal of the non-linear feedback circuit is connected to the output terminal of the amplifier circuit and the output terminal of the non-linear feedback circuit is connected to the amplifier circuit to reduce the gain of the amplifier circuit when an RF voltage swing present at the input terminal of the non-linear feedback circuit exceeds a predefined threshold. In one embodiment, the output terminal of the non-linear feedback circuit is connected to the input terminal of the amplifier circuit. In another embodiment, the output terminal of the non-linear feedback circuit is connected to a bias circuit of the amplifier circuit.