Apparatus and methods for envelope tracking systems are provided. In certain configurations, an envelope tracking system includes a digital filter that generates a filtered envelope signal based on a digital envelope signal representing an envelope of a radio frequency signal, a buck converter controllable by the filtered envelope signal and including an output electrically connected to a power amplifier supply voltage, a digital-to-analog converter module including an output electrically connected to the output of the buck converter and that provides an output current, and a digital shaping and delay circuit configured to generate a shaped envelope signal based on shaping the filtered envelope signal. The shaped envelope signal controls a magnitude of the output current, and the digital shaping and delay circuit controls a delay of the shaped envelope signal to align the output of the digital-to-analog converter module and the output of the buck converter.

Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier that amplifies a radio frequency signal and that receives power from a power amplifier supply voltage. The power amplifier system further includes an envelope tracker that generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker includes a signal bandwidth detection circuit that processes the envelope signal to generate a detected bandwidth signal, and a mode control circuit that controls a mode of the error amplifier based on the detected signal bandwidth.

A multiple functional equivalence digital communications interface and a group of functional circuits are disclosed. The multiple functional equivalence digital communications interface presents a functional equivalence of each of a group of digital communications interfaces to a digital communications bus. Each functional equivalence of the group of digital communications interfaces is associated with a corresponding one of the group of functional circuits.

Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch.

An arrangement and method for radio-frequency (RF) high power generation which compensate for a failed power amplifier module includes at least one power combiner having RF inputs and at least one RF output, and at least two power amplifier modules electrically connected to a respective input by at least one transmission line, and at least one RF switch formed by the at least one transmission line with a complex load electrically connected to the at least one RF switch.

Power amplifier having biasing with selectable bandwidth. In some embodiments, a power amplifier can include an amplifying transistor having a base for receiving a signal to be amplified, and a bias circuit configured to bias the amplifying transistor. The bias circuit can include a reference transistor having a base coupled to the base of the amplifying transistor and a collector coupled to a reference current source. The bias circuit can further include a coupling circuit that couples the collector and the base of the reference transistor. The coupling circuit can include a switchable element configured to allow the coupling circuit to be in a first state to provide a first bandwidth for the bias circuit or a second state to provide a second bandwidth for the bias circuit.

Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies.

Disclosed are a signal processing device and an image display apparatus including the same. The signal processing device includes an amplifier to perform amplification based on an input differential signal, an output driver to output an audio output signal based on an output signal from the amplifier, a reference voltage output device to output a reference voltage in response to power ON, a pre-output driver configured to pre-compensate for an offset voltage and output a compensation signal, based on an output signal from the amplifier after the power ON, and a first switching device disposed between an output terminal of the output driver and an output terminal of the pre-output driver, wherein the output driver operates after the first switching device is turned on in response to the power ON. Accordingly, pop noise and harmonic distortion in case in which power is turned on may be reduced.

An apparatus includes an input amplifier stage and a switch that has a first terminal at a virtual ground input of the input amplifier stage.

A distributed amplification device with p inputs, p outputs, p amplification paths comprises a redundant reservoir of n amplifiers including n-p back-up amplifiers, an input redundancy ring and an output redundancy ring formed by rotary switches, the input and output redundancy rings sharing the same technology. The internal amplification pathways associated with the n-p back-up amplifiers frame in an interlaced manner the internal amplification pathways associated with the p nominal amplifiers and the amplification paths of the routing configurations each pass through at least five rotary switches. The input and output redundancy rings are topologically and geometrically configured and the family of the routing configurations is chosen such that the electrical lengths of all the paths of one and the same routing configuration of the family are equal.