Integrated filter and electromagnetic coupler assemblies. In certain examples, an integrated filter and electromagnetic coupler assembly includes a filter having a capacitance and a series inductance, the series inductance being connected between an input port and an output port of the integrated filter and electromagnetic coupler assembly, and combination of the capacitance and the series inductance being selected to provide the filter with a passband and a stopband. The integrated filter and electromagnetic coupler assembly further includes a coupling element positioned physically proximate the series inductance and extending between a coupled port and an isolation port of the integrated filter and electromagnetic coupler assembly, the integrated filter and electromagnetic coupler assembly being configured to provide at the coupled port a coupled signal via inductive coupling between the series inductance and the coupling element responsive to receiving an input signal at the input port.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.

A power amplifier system which operates at a narrow band with high power and high efficiency or at a wide band is provided. Said power amplifier system comprises at least one high power amplifier; at least one connection line; at least one input block which receives at least one signal from an input, which is connected to said high power amplifier and connection line, which sends received signal to either high power amplifier or connection line and which amplifies the power of the signal sent to the connection line; and at least one high power asymmetric output switch, which is connected to said high power amplifier and connection line and which sends signals coming from said high power amplifier and connection line to an output.

Aspects of this disclosure relate to a band pass filter that includes LC resonant circuits coupled to each other by a capacitor. A bridge capacitor can be in parallel with series capacitors, in which the series capacitors include the capacitor coupled between the LC resonant circuits. The bridge capacitor can create a transmission zero at a frequency below the passband of the band pass filter. The LC resonant circuits can each include a surface mount capacitor and a conductive trace of the substrate, and an integrated passive device die can include the capacitor. Band pass filters disclosed herein can be relatively compact, provide relatively good out-of-band rejection, and relatively low loss.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.