Apparatus and methods for envelope tracking systems are provided. In certain configurations, an envelope tracking system includes a digital filter that generates a filtered envelope signal based on a digital envelope signal representing an envelope of a radio frequency signal, a buck converter controllable by the filtered envelope signal and including an output electrically connected to a power amplifier supply voltage, a digital-to-analog converter module including an output electrically connected to the output of the buck converter and that provides an output current, and a digital shaping and delay circuit configured to generate a shaped envelope signal based on shaping the filtered envelope signal. The shaped envelope signal controls a magnitude of the output current, and the digital shaping and delay circuit controls a delay of the shaped envelope signal to align the output of the digital-to-analog converter module and the output of the buck converter.

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

Aspects of this disclosure relate to a band pass filter that includes LC resonant circuits coupled to each other by a capacitor. A bridge capacitor can be in parallel with series capacitors, in which the series capacitors include the capacitor coupled between the LC resonant circuits. The bridge capacitor can create a transmission zero at a frequency below the passband of the band pass filter. The LC resonant circuits can each include a surface mount capacitor and a conductive trace of the substrate, and an integrated passive device die can include the capacitor. Band pass filters disclosed herein can be relatively compact, provide relatively good out-of-band rejection, and relatively low loss.

A system may include a pulse-width modulation mode path configured to drive a load at an output of the system in a first mode of operation, a linear mode path configured to drive the load in a second mode of operation, a common mode control feedback loop configured to set a value of a common mode output signal at the output in the second mode of operation, and an auxiliary circuit coupled to the common mode feedback control loop and configured to maintain a state of the common mode feedback control loop during the first mode of operation as the state was or will be during the second mode of operation.

A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch.

A Class-D amplifier having a low power dissipation mode includes first and second independent output stages that receive respective first and second level power supply voltages for driving a load coupled to the amplifier output during respective first and second operating modes. Bypass switches are controllable to disconnect the second output stage from the output during the first operating mode and to connect the second output stage to the output during the second operating mode. The operating modes are selected based on the amplifier output power level. First and second independent pre-driver stages receive the respective first and second level power supply voltages for driving the respective first and second independent output stages. During the second operating mode the first pre-driver stage is placed into a low power dissipation state and during the first operating mode the second pre-driver stage is placed into a low power dissipation state.

In a Class-D amplifier, first/second ratios and first/second RC time constants are sequentially matched by trimming. An integrator is coupled to differential first/second paths. The first/second ratios are of a feedback resistor to an input resistor in the first/second paths. R's of the first/second RC time constants are the resistors of the first/second matched ratios. C's of the first/second RC time constants are integrating capacitors in the first/second path. For each of multiple power rails, a ramp amplitude is determined based on a sensed voltage. Concurrently, the driver stage is switched from first to second power rails and quantizer switched from first to second ramp amplitudes to achieve constant combined quantizer/driver stage gain. Based on a sensed load current, an IR drop is determined for a respective output impedance of the driver stage and added to a loop filter output to compensate for the respective output impedance.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A semiconductor device formed on a silicon on insulator substrate includes an input node to receive a first signal, such as a high frequency signal, and an output node to output a second signal corresponding to the first signal. A first transistor has a gate that receives the first signal from the input node and thereby outputs an amplified first signal. A second transistor is connected between a drain of the first transistor and the output node. An inductor is connected between a source of the first transistor and a ground potential. A capacitor connected is between the gate of the first transistor and the input node. An electrostatic discharge (ESD) protective element is connected between a first node and a second node. The first node is between the inductor and the first transistor, and the second node is between the input node and the capacitor.