A low noise amplifier circuit includes a first low noise amplifier including a common gate structure cascoded with a parallel common source structure to selectively amplify a band signal among first and second band signals; a second low noise amplifier including a common gate structure cascoded with a parallel common source structure to selectively amplify a band signal among third and fourth band signals; an output DPDT circuit including a first input terminal connected to the first low noise amplifier, a second input terminal connected to the second low noise amplifier, and a first output terminal and a second output terminal for selectively outputting signals input through the first input terminal and the second input terminal; and a control circuit performing an amplification control and a switching control for the first and second low noise amplifiers and the output DPDT circuit in response to a predetermined communications scheme.

Envelope trackers providing compensation for power amplifier output load variation are provided herein. In certain configurations, a radio frequency (RF) system includes an antenna, a power amplifier that receives a radio frequency signal and outputs an amplified radio frequency signal to the antenna, a plurality of detectors coupled to the power amplifier and operable to generate a plurality of detection signals, and an envelope tracker that controls a supply voltage of the power amplifier based on an envelope of the radio frequency signal. The envelope tracker processes the plurality of detection signals to generate a load variation detection signal indicating a change in an output load of the power amplifier arising from a change in a voltage standing wave ratio (VSWR) of the antenna. Additionally, the envelope tracker adjusts a gain of the power amplifier based on the load variation detection signal.

Amplifier systems for driving a wide range of loads are provided herein. In certain embodiments, an amplifier system includes a voltage output amplifier and a current output amplifier that are electrically coupled in parallel with one another between an input terminal and an output terminal. The amplifier system further includes a control circuit operable to control whether or not the voltage output amplifier and/or current output amplifier drive the output terminal.

Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier configured to provide amplification to a radio frequency signal and to receive power from a power amplifier supply voltage, and an envelope tracker including a signal bandwidth detection circuit configured to generate a detected bandwidth signal based on processing an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker further includes a switch bank configured to receive a plurality of regulated voltages, a filter configured to filter an output of the switch bank to generate the power amplifier supply voltage, and a mode control circuit configured to control a filtering characteristic of the filter based on the detected bandwidth signal.

Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.

Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures, and a power amplifier and switch can be integrated onto a single complementary metal oxide semiconductor die.

A filter includes a series arm circuit connected between an input-output terminal and an input-output terminal and a parallel arm circuit connected between a ground and a node. The parallel arm circuit includes a first circuit and a second circuit. The first circuit has a parallel arm resonator. The second circuit is connected in parallel with the first circuit and has a parallel arm resonator. At least one of the first and second circuits includes a variable frequency circuit. The variable frequency circuit is connected in series with the parallel arm resonator or the parallel arm resonator included in the corresponding one of the first and second circuits. The variable frequency circuit has an impedance element and a switch connected in parallel with each other. The parallel arm resonator has a resonant frequency different from the parallel arm resonator and an anti-resonant frequency different from the parallel arm resonator.

An operational amplifier includes: a first amplifier stage, configured to generate first output voltages according to first input voltages; a second amplifier stage, configured to generate second output voltages according to the first output voltages; a second output stage circuit, configured to replicate an equivalent or a scaled-down version of the first output stage circuit; a first common-mode feedback circuit, configured to keep an output common-mode voltage of the second output stage circuit at a predetermined value; a logic loop circuit configured to, when the operational amplifier operates in a direct current calibration phase, adjust a difference between the first output voltages; a bias circuit, configured to generate a voltage close to a common mode voltage of the first output voltages produced after the operational amplifier is turned on, the voltage serving as a reference voltage of a second common-mode feedback circuit.

A half-power buffer and/or amplifier is disclosed. The half-power buffer and/or amplifier includes an amplifying unit including first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors and to output a voltage over a first voltage range between the first and third voltages, a second output buffer unit including third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors and to output a voltage over a second voltage range between the second and third voltages, and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to perform a charge share and/or equalization operation.

A photoelectric conversion device is provided. The device comprises a light receiving element, first and second transimpedance amplifiers configured to receive a signal of the light receiving element and output a voltage, a differential operation amplifier configured to perform a differential amplification for outputs of the first and second transimpedance amplifiers and a switching unit. The switching unit includes an output switching unit configured to switch connections between a first state where the light receiving element and the first transimpedance amplifier are connected and a second state where the light receiving element and the second transimpedance amplifier are connected, and a capacitance adjusting unit connected to an input terminal of each of the first and second transimpedance amplifiers and configured to adjust a capacitance value of the first and transimpedance amplifier and/or a capacitance value of the second transimpedance amplifier.