A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more metamaterial (“MTM”) resonant circuits coupled in shunt with an RF path that couples the amplifying circuit in series and configured to establish a frequency of operation and a phase response to output a signal having RF frequencies with a ultra-wide bandwidth.

An amplifier and a method of outputting a waveform of a music signal capable of outputting a waveform of a music signal exceeding a power supply voltage is provided. An amplifier includes a power supply, an input terminal for a music signal, an amplifying circuit which amplifies the music signal using the power supply, and a jumping-up circuit which is connected to an output end of the amplifying circuit and outputs a waveform exceeding a voltage value of the power supply.

The present invention provides a circuit having a filter with an amplifier circuit for filtering and amplifying an input signal to generate an output signal, wherein a corner frequency of the filter is adjustable to control a settling time of the output signal.

A MEMS sensor (1) comprises a MEMS transducer (10) being coupled to a MEMS interface circuit (20). The MEMS interface circuit (20) comprises a bias voltage generator (100), a differential amplifier (200), a capacitor (300) and a feedback control circuit (400). The bias voltage generator (100) generates a bias voltage (Vbias) for operating the MEMS transducer. The variable capacitor (300) is connected to one of the input nodes (I200a) of the differential amplifier (200). At least one of the output nodes (A200a, A200b) of the differential amplifier is coupled to a base terminal (T110) of an output filter (110) of the bias voltage generator (100). Any disturbing signal from the bias voltage generator (100) is a common-mode signal that is divided equally on the input nodes (I200a, I200b) of the differential amplifier (200) and is therefore rejected.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x≈1.5).

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I.sub.0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.